• 한국정보통신학회논문지
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• 제9권5호
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• pp.1073-1081
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• 2005

본 논문은 상위 7비트와 하위 3비트의 segmented 전류원 구조로서 최적화 된 binary-thermal decoding 방식을 이용한 3.3v 10비트 CMOS D/A 변환기를 제안한다. segmeted 전류원 구조와 최적화 된 binary-thermal decoding 방식을 D/A 변환기가 지니므로 가질 수 있는 장점은 디코딩 논리회로의 복잡성을 단순화함으로 칩면적을 줄일 수 있다. 제안된 변환기는 0.35um CMOS n-well 표준공정을 이용하여 제작되었으며, 유효 칩면적은 $0.953mm^2$ 이다. 설계된 칩의 상승/하강시간, 정작시간 및 INL/DNL은 각각 1.92/2.1 ns, 12.71 ns, ${\pm}2.3/{\pm}0.58$ LSB로 나타났다. 또한 설계된 D/A 변환기는 3.3V의 공급전원에서는 224mW의 전력소모가 측정되었다.

• ETRI Journal
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• 제33권6호
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.673-675
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• 2004

This study proposes controller with voltage-compensated drivers for producing gray-scaled pictures on passive matrix organic light emitting diodes (PMOLEDs) panels. The controller includes voltage type drivers so the output impedance of the driver is far less than that of the current-type driver. Its low output impedance provides better electron-optical properties than those of traditional current drivers. A free running clock and a group of counters are applied to the gray-scaled function so that phase lock loop (PLL) circuit can be reduced in the controller. A pre-charge function is used to enhance performance of the luminance of an active OLED pixel. As a result, distribution of the low gray level portion is achieved linear relationship with input data. In this work, the digital part of the proposed controller is implemented using FPGA chips, and analog parts are combined with a digital-analog converter (DAC) and analog switches. A still image is displayed on a $48^{\ast}64$ PMOLEDs panel to assess the luminance performance fir the controller. Based on its cost requirement and luminance performance, the controller is qualified to join the market for driving PMOLEDs panels.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.11-14
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• 2003

A silicon based OELD driving circuit that has a new type of column driving method is proposed to reduce the driving circuit area. In comparison with the conventional method, latches in each column are removed and one DAC (digital-to-analog converter) drives several column lines. To make the DAC operate during a specific period for the low power consumption, a simple DESG (DAC Enable Signal Generator) circuit was devised and confirmed by the simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• Journal of electromagnetic engineering and science
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• 제1권2호
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• pp.131-138
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• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• 한국항행학회논문지
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• 제16권2호
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• pp.351-359
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• 2012

본 논문에서는 CDMA 데이터 모뎀을 이용하여 원격에서 다양한 입출력 장치들의 상태를 계측하거나 이들을 제어하는 시스템을 설계하고 개발한다. 그리고 TCP/IP 패킷 통신과 단문자서비스(SMS) 통신방식을 이용하여 공인 IP 주소를 갖지 않는 CDMA 모뎀 장치들을 위한 양방항 데이터 통신 방식을 제안한다. 설계된 원격 제어 및 계측시스템은 DCE로 Telit WM-800 모뎀과 DTE로서 Atmel AT89C51 마이크로컨트롤러를 사용하여 구현되었다. 제어 및 계측 시스템 사용자를 위한 사용자 응용 프로그램, 그리고 디지틀 입출력 장치, AD/DAC, LCD, 및 온습도 센서 등의 펌웨어 구동장치 프로그램은 보다 다양한 종류의 응용을 위하여 각각 Microsoft C 및 Keil C 언어를 사용하여 작성되었다. 본 논문에서 구현된 제어 및 계측 시스템의 실험결과는 실제 실시간 실험을 통해, 설계된 바와 같이 사용자가 원하는 동작을 정확하게 수행하는 것을 확인하였다.

• 반도체공학회 논문지
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• 제2권3호
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• pp.13-18
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• 2024

본 논문은 Reference generator 와 Comparator 에서 발생하는 offset 을 최소화하고 정확도를 향상시키기 위해 Auto zero 기술을 활용한 회로를 제안한다. 이에 대한 근거로 Auto zero 사용 전/후를 비교했을 때 약 90% 표준 편차가 줄어드는 결과를 얻을 수 있었다. 제안하는 회로는 55nm CMOS 공정을 사용하였으며, input frequency 는 781.2 Hz, Effective Number of Bits(ENOB) 8.01bit, Signal-to-Noise Distortion Ratio(SNDR)이 49.98dB 을 보여준다.

• 센서학회지
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• 제25권5호
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.