• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.219-222
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• 2003

The Capacitor DAC with gamma correction is proposed for TFT-LCD (Liquid Crystal Display) driver application. It is based on two ideas. First, 6bit digital code is converted 8bit digital code by memory circuit (Look Up Table) for gamma correction. second, weighted voltage ratio DAC is proposed for reducing area and power consumption.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.11
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• pp.61-66
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• 2005

This paper describes a 10-bit 210MHz CMOS current-mode Digital-to-Analog Converter (DAC) consisting of 6 bit MSB current cell matrix Sub-DAC, 2 bit mSB unary current source Sub-DAC, and 2 bit LSB binary weighting Sub-DAC for Wireless LAN application. A new deglitch circuit is proposed to control a crossing point of signals and minimize a glitch energy. The proposed 10-bit CMOS current mode DAC was designed by a $0.35{\mu}m$ CMOS double-poly four-metal technology rate of 210MHz, DNL/INL of ${\pm}0.7LSB/{\pm}1.1LSB$, a glitch energy of $76pV{\cdot}sec$, a SNR of 50dB, a SFDR of 53dB at 200MHz sampling clock and power dissipation of 83mW at 3.3V

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1578-1581
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• 2009

This work describes a power and area efficient switched-capacitor cyclic DAC for mobile display drivers. The proposed DAC can be simply implemented with one opamp two capacitors and several switches. Furthermore, the op-amp input referred offset is attenuated at the DAC output without additional offset cancellation circuitry. The operation of the cyclic DAC is verified through circuit level simulations.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.685-691
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, considering linearity, power consumption, chip area, and glitch energy. The low-glitch switch driving circuit is employed to improve the linearity and the dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core. The prototype DAC is implemented in a 0.35 urn n-well single-poly quad-metal CMOS technology. The measured DNL and INL of the prototype DAC are within $\pm$0.75 LSB and $\pm$1.73 LSB, respectively, and the spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of 2.2 mm ${\times}$ 2.0 mm.