• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.968-971
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• 1993

Fuzzy inference system which inferences and processes the Fuzzy information is designed using digital voltage mode neural circuits. The digital fuzzification circuit is designed to MIN,MAX circuit using CMOS neural comparator. A new defuzzification method which uses the center of area of the resultant fuzzy set as a defuzzified output is suggested. The method of the center of area(C. O. A) search for a crisp value which is correspond to a half of the area enclosed with inferenced membership function. The center of area defuzzification circuit is proposed. It is a simple circuit without divider and multiflier. The proposed circuits are verified by implementing with conventional digital chips.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.2944-2946
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• 1999

In this paper, digital circuit evolution is proposed as an intrinsic evolvable system. Evolutionary hardware is a reconfigurable one which adapt itself to the environment and evolve its structure to realize desired performance. By using special FPGA and genetic algorithm, we have made a prototype of intrinsic hardware evolution system. As an example for digital circuit evolution, full adder realization is performed. As the result of this, a very complex structure of digital circuit performing full adder was created. Analysis made on the hardware revealed that some undetermined circuits were developed.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 하계종합학술대회논문집
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• pp.65-68
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, this proposed Digital-Radio conversion system is called D/R converter, and the principle of this D/R converter, radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Journal of Multimedia Information System
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• 제6권4호
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• pp.323-328
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• 2019

In this paper, a method of constructing an advanced sequential circuit over finite fields is proposed. The method proposed an algorithm for assigning all elements of finite fields to digital code from the properties of finite fields, discussed the operating characteristics of T-gate used to construct sequential digital system of finite fields, and based on this, formed sequential circuit without trajectory. For this purpose, the state transition diagram was allocated to the state dependency code and a whole table was drawn showing the relationship between the status function and the current state and the previous state. The following status functions were derived from the status function and the preceding table, and the T-gate and the device were used to construct the sequential circuit. It was confirmed that the proposed method was able to organize sequential digital systems effectively and systematically.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.107.1-107
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• 2001

In this paper, a digital signal processing circuit for Position Sensitive Detectors(PSDs) is introduced to substitute the conventional analog signal processing circuit and to compensate disadvantages of the PSD. In general, the analog circuits have the problems such as noise accumulation, sensitivity for environmental changes, and high cost for manufacturing. Moreover, the intrinsic nonlinearity problem of the PSD makes it hard to measure the position accurately because it is difficult to be overcome the problem by using the conventional analog circuits, which can be solved by using the digital signal processing circuit. The circuit is implemented by using a Field Programmable Gate Array (FPGA). The Pulse Amplitude Modulation(PAM) method is used for reducing the environmental noise effect, and a linear interpolation logic is used to compensate the ...

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.441-442
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• 2012

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.333-336
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• 2001

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

• 한국인터넷방송통신학회논문지
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• 제9권1호
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• pp.89-94
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• 2009

본 논문에서는 경로수 ${\zeta}$로 주어진 DCG(Directed Cyclic Graph)의 입출력간의 연관관계를 고효율디지털논리회로로 설계하는 알로리즘과 DCG의 각 노드들에 코드를 할당하는 알고리즘을 제안하였다. 본 논문에서는 기존 알고리즘의 문제점을 도출한 후, 다른 접근방법으로써 DCG의 경로수로 부터 행렬방정식을 유도한 후 이를 통해 DCG의 경로수에 따른 회로설계 알리즘을 제안하였으며, 설계된 회로와 함께 DCG의 특성을 만족하도록 노드들에 대한 코드를 할당하는 알고리즘을 제안하였다. 본 논문에서 제안한 고효율디지털논리회로설계 알고리즘은 기존의 알고리즘으로는 가능하지 않았던 경로수의 DCG에 대하여 회로설계가 가능하게 되었고, 보다 최적화된 디지털논리회로를 구현할 수 있음을 확인하였다. 본 논문에서 제안한 회로설계 알고리즘을 통해 임의의 자연수를 경로수로 갖는 DCG에 대한 설계가 가능하며, 입출력단자 수의 감소. 회로구성의 간략화, 연산속도의 향상과 비용감소 등의 잇점이 있고, 예제를 통해 본 논문에서 제안한 알고리즘의 적합성과 타당성을 검증하였다.

• 대한전자공학회논문지SD
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• 제46권6호
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• pp.31-38
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• 2009

휴대용 기기의 소비 전력을 낮추고 영상의 질을 개선하기 위해, 주변 밝기에 따라서 LCD 모듈의 백라이트를 조정하는 방법을 사용할 수 있다. 이를 효과적으로 구현하기 위해서 LCD 패널에 광 센서와 신호취득 회로를 집적하고자 했으며, LTPS TFT 공정을 이용하여 설계했다. 서로 다른 LCD 패널의 광 센서에 대한 특성 편차를 보정하기 위해 새로운 개념의 start-up 보정 방식을 제안하였다. 이와 더불어 광 전류 정보를 디지털 형태로 전달하기 위해 time-to-digital 방식을 사용하였으며, 이를 start-up 보정 방식과 효과적으로 결합하는 dual slope 보정 방법을 제안하였다. LTPS TFT 공정을 이용하여 최종적인 신호취득 회로를 구현하고자, 간단하고 안정적인 회로 구조와 타이밍을 제안하고 설계 및 검증을 진행했다. 설계한 신호취득 회로는 별도의 검사 설비 없이 광 센서 편차의 보정이 가능하며, 60dB 범위의 입력 광에 대해 10배수 구간 마다 4 단계의 디지털 데이터를 출력한다. 신호취득 속도는 100Hz이며, 디지털 변환의 선형 오차는 18% 미만이다.

• KIEE International Transactions on Electrophysics and Applications
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• 제3C권6호
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.