• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.146-148
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• 2006

The aim of the paper is to design the PLS(Plasma Lighting System) driving inverter circuit with optimal efficiency. In general, it is known that the PLS driven by a pulse has a higher light-conversion efficiency. There are the Class-E type resonant inverter and the semi-bridge inverter as a circuit which can make a pulse with low duty ratio. In this paper, we analyze the losses of the above two circuits. To verify the loss analysis, the inverter circuit with 220V 380W input consumption is manufactured and tested. Throughout the experimental results, the high efficiency PLS system has confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1130-1133
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• 2021

In this paper, a miniaturized sensor interface circuit for the respiration detection system is proposed. Respiratory diagnosis is one of the main ways to predict various diseases. The proposed system consists of respiration detection sensor, temperature sensor, and interface circuits. Electrochemical type gas sensor using solid electrolytes is adopted for respiration detection. Proposed system performs sensing, amplification, analog-to-digital conversion, digital signal processing, and i2c communication. And also proposed system has a small form factor and low-cost characteristics through optimization and miniaturization of the circuit structure. Moreover, technique for sensor degradation compensation is introduced to obtain high accuracy. The size of proposed system is about 1.36 cm².

• Journal of IKEEE
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• v.16 no.1
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• pp.20-27
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• 2012

In order to overcome jamming, a hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested, designed, fabricated, measured and analyzed in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. An improved variable hysteresis comparator circuit controlled by serial digital bits is suggested, designed and simulated to overcome jamming in modern warfare.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.7
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• pp.2570-2578
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• 2010

This paper presents a digital-controlled single-phase power-factor correction (PFC) converter operating in critical current conduction mode. The proposed converter utilizes the DC-DC boost converter topology for the PFC and operates the inductor current in critical conduction mode. Because the proposed converter is controlled digitally using a micom, its control circuit is simplified and the converter operates more effectively. This paper first explains the operational principles of the proposed converter and then analyzes the converter circuit. And this paper explains the implementation method of proposed converter with a detail design example, which is divided into software and circuit design parts. Also, it is shown through the experimental results of the prototype converter by the designed circuit parameters that the proposed converter has good performance as a single-phase PFC converter.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.20-23
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• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Journal of Power Electronics
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• v.9 no.6
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• pp.903-910
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• 2009

In this paper, a digital average current mode control using diode current sensing technique is proposed. Although the conventional inductor current sensing technique is widely used, the sensed signal of the current is negative. As a result, it requires an additional circuit to be applied to general digital controller ICs. The proposed diode current sensing method not only minimizes the peripheral circuit around the digital IC but also consumes less power to sense current information than the inductor current sensing method. The feasibility of the proposed technique is verified by experiments using a 500W power factor correction (PFC) boost rectifier.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.5-5
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• 2001

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.7
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• pp.393-400
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• 2003

This paper discusses how to implement and verify a software model of the digital relay that can be added to real time digital simulator(RTDS) model library and is then subjected to the same outputs as the actual relay. The software model is stand-alone and can be used with real relays. It is also possible to conduct interactive real-time tests when the system effects of the relay action need to be investigated. The characteristics of mho type and the quadrilateral type, which is commonly used in recently developed relays, are modeled in this paper. Single circuit line and double circuit line system are used for model verification. The transmission lines are each 100 km in length and are modeled as distributed parameter lines but not frequency dependent. The transmission lines in the single circuit system are modeled as ideally transposed line. The mutual coupling data with the parallel line was taken account in the transmission lines for the double circuit system. The main CTs and PTs are included and operated in their linear region during the tests. For the purpose of testing the relay model accuracy the faults have been applied at various points on the protected line. Its accuracy is assessed against theoretical values.