• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• Journal of Semiconductor Engineering
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• 제1권3호
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• 전기전자학회논문지
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• 제9권1호
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• pp.65-71
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• 2005

실세계에서 발생하는 물리적인 신호는 센서를 통하여 전기적 신호로 바뀌어 전자회로에 입력된다. 입력된 전기적 신호는 아날로그 형태인데 디지털 신호처리를 위해서 아날로그-디지털 변환기 (ADC Analog-Digital Converter)를 사용하여 디지털 신호로 변환시켜야 한다. 실리콘 마이크로 센서와 결합되어 사용되는 신호처리 회로 및 ADC는 단일칩에 구현되기 용이하도록 저전력 및 소면적으로 설계되어야 한다. 본 논문에서는 실리콘 마이크로센서와 단일칩에 구현하기 적합하도록 실리콘 사용 면적을 대폭 줄인 전하재분배 방식의 ADC를 설계하였다. 설계된 방식은 4 비트 변환을 두 차례 수행하여 8 비트 변환을 하는 방식으로 기존 방식에 비해 커패시터 어레이의 면적을 1/16로 줄였다. 연적을 줄인 대신 변환에 사용된 클럭의 수는 2배 정도 증가되었으나 압력센서의 신호는 고속 변환이 요구되지 않으므로 압력센서에 적합하다고 할 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.5-8
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• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.

• 한국통신학회논문지
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• 제16권4호
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• pp.301-308
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• 1991

본 연구에서는 라디오 데이타 수신 시스템의 복조 회로를 제안하고, 잡음에 모험된 디지탈 전송 신호의 오차확률을 구하여, 그의 성능을 평가하였다.일반적인 논리회로와 PLL을 이용하여 수신 복조회로를 설계 및 구현하였으며, 이것을 이요 여 라디오 데이터 수신 시스템의 새로운 집적회로 설계가 가능하도록 하였다. 또한 복원된 디지탈 신호의 오율특성을 계산하여 기존의 복조회로와 등가의 성능임을 확인하였다.임을 확인하였다.

• ETRI Journal
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• 제43권4호
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• pp.728-745
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• 2021

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.

• 전자통신동향분석
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• 제3권4호
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• pp.114-130
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• 1988

본 고에서는 GaAs DIC (Digital Integrated Circuits)의 최근 연구경향을 공정기술을 중심으로 소개한다. GaAs DIC의 역사, 공정, 설계, 집적도에 대하여 살펴봄으로써 초고속 GaAs DIC 개발의 향후 방향을 모색하고자 한다. 본 고는 1987년 SPIE지에 게재된 일본 NTT연구소의 Hirayama와 Ikegami의 논문 내용을 중심으로 편역한 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of Communications and Networks
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• 제12권6호
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• pp.558-567
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• 2010

In this paper, we analyze the capability of satellite broadcasting systems to offer different levels of quality of service (QoS). We focus on the European telecommunications standards institute satellite digital radio and digital video broadcasting satellite handheld (DVB-SH) standards, which have recently been proposed for satellite broadcasting communications. We propose a strategy to provide different levels of QoS for the DVB-SH standard on the basis of an extension of the interleaving scheme, referred to as molded interleaver, which supports low latency service requirements for interactive services. An extensive analysis based on laboratory measurements shows the benefits of this solution. We also present a multilevel coding (MLC) scheme with multistage decoding designed for broadcasting communications as an alternative to the existing standards, where services with different levels of QoS are provided. We present a graphical method based on mutual information for the design and evaluation of MLC systems used for broadcasting communications. Extensive simulations for a typical satellite channel show the viability of the proposed MLC scheme. Finally, we introduce multidimensional constellations in the proposed MLC scheme in order to increase the number of different protection levels.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2009년도 추계학술발표논문집
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• pp.636-639
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• 2009

In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.