• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.12
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• pp.5647-5654
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• 2012

In this paper, we developed an electro impedance spectroscopy (EIS) device, which are primarily used for the analysis of fuel cells or batteries, to widen its coverage to the next generation super capacitor EDLC characterization. The developed system was composed of a signal generator that can generate various signal patterns, a potentiostatic generator, and a high speed digital filter for signal processing and measurement program. The developed system is portable, which is not only suitable laboratory use but also for mass production line. The special features of the system include a patterned output signal from 0.01 to 20 kHz, and a fast Fourier transform (FFT) analysis of current signals, both of which are acquired simultaneously. Our tests showed similar results after comparing the analysis from our newly-developed device showing the characteristics of EDLC complex impedance and the analysis from an equivalent impedance which was applied to an equivalent circuit. Now, we can expect a fast inspection time from the application of the present system to the super capacitor production line, based on time-varying changes in electrochemical impedance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2
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• pp.50-61
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• 1995

A time scale modification method yielding rate-modified speech while conserving the characteristic of speech was implemented in real-time using a goneral purpose digital signal processor. Time scale modification changed pronunciation speed only, producing a time difference between the input signal and the modified signal, making it impossible to implement it in real-time. In this thesis, a system was implemented to remove the time difference between the input and modified signals. Speech signals slowed down or speeded up by a physical time scale modification method, such as adjusting the motor speed of the cassett tape recorder, was used as the input signal. Physical modification that controled only the inter speed of the cassette tape player distorted the pitch period of the original speech. In this study, a real-time system was implemented so that the pitch-distorted speech was reconstructed back to the original by fractional sampling pitch shifting using an FIR filter, and this signal was time scale modified to match the cassette tape recorder motor speed using SOLA time-scale medification. In experiments using speech signals medifiedby the proposed method, results obtained using a 16-bit resolution ADSP2101 processor and using computer simulations employing floating point operations showed about the same average frame signal-to-noise ratio of about 20 dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.181-187
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• 2020

In this paper, we proposed a register allocation algorithm and resource allocation algorithm in the high level synthesis process for the SoC design synthesis system of high performance vehicles We have analyzed to the operator characteristics and structure of datapath in the most important high-level synthesis. We also introduced the concept of virtual operator for the scheduling of multi-cycle operations. Thus, we demonstrated the complexity to implement a multi-cycle operation of the operator, regardless of the type of operation that can be applied for commonly use in the resources allocation algorithm. The algorithm assigns the functional operators so that the number of connecting signal lines which are repeatedly used between the operators would be minimum. This algorithm provides regional graphs with priority depending on connected structure when the registers are allocated. The registers with connecting structure are allocated to the maximum cluster which is generated by the minimum cluster partition algorithm. Also, it minimize the connecting structure by removing the duplicate inputs for the multiplexor in connecting structure and arranging the inputs for the multiplexor which is connected to the operators. In order to evaluate the scheduling performance of the described algorithm, we demonstrate the utility of the proposed algorithm by executing scheduling on the fifth digital wave filter, a standard bench mark model.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.421-432
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• 2020

This paper proposes a 2-kW solid-state power amplifier (SSPA) developed by employing power amplifier pallets designed using gallium-nitride high electron mobility transistors, which is used in S-band military radars and to replace existing traveling-wave tube amplifier (TWTA). The SSPA consists of a high-power amplifier module, which combines eight power amplifier pallets, a drive amplifier module, a digital control module, and a power supply unit. First, the amplifier module and component were integrated into a small package to account for space limitations; next, an on-board harmonic filter was fabricated to reject spurious components; and finally, an auto gain control system was designed for various duty ratios because recent military radar systems are all active phase radars using the pulse operation mode. The developed SSPA exhibited a max gain of 48 dB and an output power ranging between 63-63.6 dBm at a frequency band of 3.1 to 3.5 GHz. The auto gain control function showed that the output power is regulated around 63 dBm despite the fluctuation of the input power from 15-20 dBm. Finally, reliability of the developed system was verified through a temperature environment test for nine hours at high (55 ℃) / low (-40℃) temperature profile in accordance with military standard 810. The developed SSPA show better performance such as light weight, high output, high gain, various safety function, low repair cost and short repair time than existing TWTA.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.773-787
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• 2006

An airborne radar is an essential aviation electronic system for the aircraft to perform various civil and/or military missions in all weather environments. This paper presents the design, development, and test results of the multi-mode X-band pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRUs(Line-Replacement Unit), which include antenna unit, transmitter and receiver unit, radar signal & data processing unit and display Unit. The developed core technologies include the planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, MTI, DSP based Doppler FFT filter, adaptive CFAR, moving clutter compensation, platform motion stabilizer, and tracking capability. The design performance of the developed radar system is verified through various ground fixed and moving vehicle test as well as helicopter-borne field tests including MTD(Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

• Journal of the Korean Society for Nondestructive Testing
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• v.33 no.5
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• pp.465-471
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• 2013

A steam generator in nuclear power plant is a heatexchager which is used to convert water into steam from heat produced in a nuclear reactor core, and the steam produced in steam generator is delivered to the turbine to generate electricity. Because of damage to steam generator tubing may impair its ability to adequately perform required safety functions in terms of both structural integrity and leakage integrity, eddy current testing is periodically performed to evaluate the integrity of tubes in steam generator. This assessment is normally performed during a reactor refueling outage. Currently, the eddy current testing for steam generator of nuclear power plant in Korea is performed in accordance with KEPIC & ASME Code requirements, the eddy current testing system is consists of remote data acquisition unit and data analysis program to evaluate the acquired data. The KEPIC & ASME Code require that the electrical properties of remote data acquisition unit, such as total harmonic distortion, input & output impedance, amplifier linearity & stability, phase linearity, bandwidth & demodulation filter response, analog-to-digital conversion, and channel crosstalk shall be measured in accordance with the KEPIC & ASME Code requirements. In this paper, the measurement requirements of electrical properties for eddy current testing instrument described in KEPIC & ASME Code are presented, and the measurement results of newly developed eddy current testing instrument by KHNP(Korea Hydro & Nuclear Power Co., LTD) are presented.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.2
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• pp.81-89
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• 2008

Wideband speech, characterized by a bandwidth of about 7 kHz (50-7000 Hz), provides a substantial quality improvement in terms of naturalness and intelligibility. Although higher data rates are required, it has extended its application to audio and video conferencing, high-quality multimedia communications in mobile links or packet-switched transmissions, and digital AM broadcasting. In this paper, we present a new bandwidth-scalable coder for wideband speech and audio signals. The proposed coder spits 8kHz signal bandwidth into two narrow bands, and different coding schemes are applied to each band. The lower-band signal is coded using the ITU-T G.729/G.729E coder, and the higher-band signal is compressed using a new algorithm based on the gammatone filter bank with an invertible auditory model. Due to the split-band architecture and completely independent coding schemes for each band, the output speech of the decoder can be selected to be a narrowband or wideband according to the channel condition. Subjective tests showed that, for wideband speech and audio signals, the proposed coder at 14.2/18 kbit/s produces superior quality to ITU-T 24 kbit/s G.722.1 with the shorter algorithmic delay.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.12
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• pp.452-458
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• 2017

In this study, a device was developed for diagnosing depression using EEG signals from July 2016 to June 2017. For normal people, the left alpha rhythm is more activated than the right alpha rhythm, but for the depressed patients, the right alpha rhythm is more activated than the left one. An analog circuit and digital low pass filter were used for noise removal and amplification of EEG, and the Hamming window function was applied to eliminate the signal leakage generated by the fast Fourier transform. To verify the validity of the developed diagnosis system, the EEG of 20 university students in the 3rd and 4th grade with an average age of 24 years was measured. Calculations of the relative value of the left and right alpha rhythm for the depression diagnosis revealed a minimum, maximum, and mean value of 66.7, 113.3, and 92.2, respectively. In addition, 7 out of 20 subjects were between 90 and 95, and those with a higher mean deviation of approximately 20 tended to have mild depression. These results can provide meaningful data for the development of depression treatment equipment by solving the left and right brain asymmetry problem, and it may be applied usefully to diagnose depression after clinical trials on a large number of depressed patients.