• 대한전자공학회논문지SD
• /
• 제46권6호
• /
• pp.25-30
• /
• 2009

본 논문에서는 터치키에 응용할 수 있는 풀 디지털 방식의 정전용량 센싱 기법을 제안한다. 제안된 회로는 측정하고자 하는 정전용량 두 개와 두 정전용량 사이 저항으로 구성된다. 각 정전용량과 저항으로 지연을 측정한 후 두 지연의 차이로 측정하고자 하는 두 정전용량의 차이를 구하는 방식으로 동작전압, 온도, 습도와 같은 동작환경변화의 영향을 완화시킬 수 있는 장점이 있다. 실험결과 제안된 방식의 정전용량 해상도가 1.02pF이어서 터치키에 적용할 수 있음을 보였다.

• Agribusiness and Information Management
• /
• 제5권1호
• /
• pp.31-41
• /
• 2013

The research assesses the impact of a digital procurement (e-purjee) system for sugarcane growers in Bangladesh. The system itself is simple, transmitting purchase orders to local farmers via SMS text notification. It replaces a traditional paper-based system fraught with low reliability and delivery delays. Applying expected value theory, and using decision tree representations to depict growers' decision-making complexity in an information-asymmetric environment, we compute outcomes for the strategies and sub-strategies of ICT vs. traditional paper-based order management from the sugarcane growers' perspective. The study results show that the digital procurement system outperforms the paper-based system by tangibly reducing growers' economic losses. The digital system also appears to benefit growers non-monetarily, because of reduced uncertainty and a higher level of perceived fairness. Sugarcane growers appear to value the non-monetary benefits even higher than the economic advantages of the e-purjee system.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2005년도 ICCAS
• /
• pp.190-195
• /
• 2005

The hearing aid chip described in this paper is an analog & digital mixed system. The design focuses on the$\mu$DSP core. This $\mu$DSP core includes internal time delays to two inputs from front and rear microphones. The paper consists of two parts; one is the composure and signal processing algorithm of digital hearing aids and the other is Verilog HDL codes for$\mu$DSP cores. All digital modules in the design were coded and synthesized by Verilog HDL codes which were verified by Mentor Graphics and Synopsis semiconductor chip design tools.

• 한국산업정보학회논문지
• /
• 제7권2호
• /
• pp.74-81
• /
• 2002

다중경로발생기는 일반적으로 시간지연발생부, 위상발생부, 감쇠발생부로 구성되며 주로 애널로그 방식으로 구현되어왔다. 따라서 경년변화가 발생할 수 있으며 여러 번의 A/D 변환, D/A변환과정으로 인한 신호의 충실도 저하, 미세지연을 위해 높은 주파수를 필요로 하는 단점이 있다. 본 논문은 다중경로 현상을 수학적으로 모델링하여 완전히 디지털 방식으로 구현하는 방법을 제안한다. 특히 시간지연부는 두 개의 블록으로 나누어 한 블록에서는 샘플단위의 시간지연을 만들고 나머지 한 블록에서는 섭샘플(subsample) 시간지연을 만들 수 있도록 하여 정밀한 시간지연값을 효율적으로 얻을 수 있도록 했다. 또한 시스템의 마스터 주파수도 특정한 값으로 고정할 필요도 없도록 하였다. 제안한 방법을 완전히 디지털 하드웨어로 구현해 본 논문에서 제안한 다중경로 발생 알고리듬의 타당성을 검증하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 하계학술대회 논문집 D
• /
• pp.2242-2244
• /
• 2003

This paper considers a networked control system (NCS) that consists of an inverted cart pendulum, a digital controller, and a controller area network (CAN) in which the actuator and sensors of the pendulum are connected to form a closed-loop system. The worst-case message response time (WCMRT) in the CAN is analyzed and the analysis results are applied to the target control system. For the case where the control system cannot satisfy the WCMRT condition and therefore time delays are inevitable, the Luck and Ray method is used to compensate the network-induced time delays. Simulations are carried out to show the feasibility of the proposed scheme.

• Journal of Power Electronics
• /
• 제13권4호
• /
• pp.600-608
• /
• 2013

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

• 한국통신학회논문지
• /
• 제21권7호
• /
• pp.1777-1786
• /
• 1996

This paper describes theories and implementation techniques of a digital high-definition television(HDTV) modem based on 32-QAM for terrestrial broadcasting. We proposed a digital demodulation scheme and a symbol timing recovery structure based on the band edge component maximization(BECM) method. The adaptive equalizer has 256 complex taps to remove the multipath of delays ranging from -2.mu.s~+24.mu.s with a new T/2-spaced blind equalization algorithm. computer simulation results reveal that the proposed algorithm outperforms other conventional blind equalization algorithm a digital HDTV modem with 4.91MHz symobol rate is implemented by utilizing the proposed algorithms. All processings for modem operations such as demodulation, estimation of symbol timing phase error, adaptive equalization, and carrier recovery except IF signal processing and sampling phase control part of the AD converter are done in digital domain. Especially, the carrier recovery loop can track a carrier offset of upto .+-.350KHz.

• 대한의용생체공학회:의공학회지
• /
• 제15권3호
• /
• pp.281-288
• /
• 1994

In this paper, a new decomposition method of the interference EMG signal using MAMDF filtering and digital signal processor. The efficient software and hardware signal processing techniques are employed. The MAMDF filter is employed in order to estimate the presence and likely location of the respective templates which may include in the observed mixture, and high-resolution waveform alignment is employed in order to provide the optimal combination set and time delays of the selected templates. The TMS320C25 digital signal processor chip is employed in order to execute the intensive calculation part of the software. The method is verified through a simulation with real templates which are obtain ed from needle EMG. As a result, the proposed method provides an overall speed improvement of 32-40 times.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.346-351
• /
• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.

• 한국측량학회:학술대회논문집
• /
• 한국측량학회 2002년도 창립 20주년기념 국제학술대회
• /
• pp.67-75
• /
• 2002

수치항공사진측량법은 지속적인 컴퓨터공학의 발전으로 인해 측량분야에 있어 발전적인 방법중의 하나로 대두되었다. 현재의 수치항공사진측량은 많은 측정장비와 검사법을 활용할 수 있다는 장점을 지니고 있다. 하지만 자동화의 측면에서 볼 때 완전히 개발된 상태라고 할 수는 없다. 기존의 항공사진측량 순서에 따른 작업흐름은 지상기준점 측량, 판독 및 지적정보취득 등 외업의 작업량에 따라 지연되어진다. 이에 공정의 간소화를 연구함으로서 수치도화법 경제적 활용가능성을 타진할 수 있다. 이에 본 연구는 새로운 작업흐름 개발과 알고리즘 연구에 초점을 두었다. 본 연구결과 경제적인 비용절감과 지형 및 지적도 제작의 기술증진에 의 효과를 얻을 수 있다.