• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1448-1452
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• 2004

In this paper, a photodiode capable of obtaining a sufficient photo/ dark current ratio at both a forward bias state and a reverse bias state is proposed. The photodiode includes a glass substrate, an Cr thin film formed as a lower electrode over the glass substrate, Cr silicide thin film(∼l00$\AA$) ) formed as a schottky barrier over the Cr thin film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the Cr silicide thin film. Transparent conduction film ITO (thickness 100nm) formed as an upper electrode over the hydro-generated amorphous silicon film is then deposited in pure argon at room temperature for the Schottky contact and light window. The high quality Cr silicide thin film using annealing of Cr and a-Si:H is formed and analyzed by experiment. We have obtained the film with a superior characteristics. The dark current of the ITO/a-Si:H Schottky at a reverse bias of -5V is ∼3$\times$IO-12 A/un2, and one of the lowest reported, hitherto. AES(Auger Electron Spectroscophy) measurements indicate that this notable improvement in device characteristics stems from reduced diffusion of oxygen, rather than indium, from the ITO into the a-Si:H layer, thus, preserving the integrity of the Schottky interface. The spectral response of the photodiode for wavelengths in the range from 400nm to 800nm shows the expected behavior whereby the photocurrent is governed by the absorption characteristics of a-Si:H.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.6
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• pp.1056-1063
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• 2006

Thermal evaporated 10 nm-Ni/l nm-Ir/(or polycrystalline)p-Si(100) and 10 nm-$Ni_{50}Co_{50}$/(or polycrystalline)p-Si(100) films were thermally annealed using rapid thermal annealing fur 40 sec at $300{\sim}1200^{\circ}C$. The annealed bilayer structure developed into Ni(Ir or Co)Si and resulting changes in sheet resistance, microstructure, phase and composition were investigated using a four-point probe, a scanning electron microscopy, a field ion beam, an X-ray diffractometer and an Auger electron spectroscope. The final thickness of Ir- and Co-inserted nickel silicides on single crystal silicon was approximately 20$\sim$40 nm and maintained its sheet resistance below 20 $\Omega$/sq. after the silicidation annealing at $1000^{\circ}C$. The ones on polysilicon had thickness of 20$\sim$55 nm and remained low resistance up to $850^{\circ}C$. A possible reason fur the improved thermal stability of the silicides formed on single crystal silicon substrate is the role of Ir and Co in preventing $NiSi_2$ transformation. Ir and Co also improved thermal stability of silicides formed on polysilicon substrate, but this enhancement was lessened due to the formation of high resistant phases and also a result of silicon mixing during high temperature diffusion. Ir-inserted nickel silicides showed surface roughness below 3 nm, which is appropriate for nano process. In conclusion, the proposed Ir- and Co- inserted nickel silicides may be superior over the conventional nickel monosilicides due to improved thermal stability.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.6
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• pp.235-242
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• 2018

High temperature electrical conductivity of Aluminum Nitride (AlN) ceramics sintered with $Y_2O_3$ as a sintering aid has been investigated with respect to various sintering conditions and MgO-dopant. When magnesium oxide is added as a dopant, liquid glass-film and crystalline phases such as spinel, perovskite are formed as second phases, which affects their electrical properties. According to high temperature impedance analysis, MgO doping leads to reduction of activation energy and electrical resistivity due to AlN grains. On the other hand, the activation energy and electrical resistivity due to grain boundary were increased by MgO doping. This is a result of the formation of liquid glass film in the grain boundary, which contains Mg ions, or the elevation of schottky barrier due to the precipitation of Mg in the grain boundary. For the annealed sample of MgO doped AlN, the electrical resistivity and activation energy were increased further compared to MgO doped AlN, which results from diffusion of Mg in the grains from grain boundary as shown in the microstructure.

• Korean Journal of Materials Research
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• v.19 no.2
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• pp.61-67
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• 2009

Electrolessly deposited Co (Re,P) was investigated as a possible capping layer for Cu wires. 50 nm Co (Re,P) films were deposited on Cu/Ti-coated silicon wafers which acted as a catalytic seed and an adhesion layer, respectively. To obtain the optimized bath composition, electroless deposition was studied through an electrochemical approach via a linear sweep voltammetry analysis. The results of using this method showed that the best deposition conditions were a $CoSO_4$ concentration of 0.082 mol/l, a solution pH of 9, a $KReO_4$ concentration of 0.0003 mol/l and sodium hypophosphite concentration of 0.1 mol/L at $80^{\circ}C$. The thermal stability of the Co (Re,P) layer as a barrier preventing Cu was evaluated using Auger electron spectroscopy and a Scanning calorimeter. The measurement results showed that Re impurities stabilized the h.c.p. phase up to $550^{\circ}C$ and that the Co (Re,P) film efficiently blocked Cu diffusion under an annealing temperature of $400^{\circ}C$ for 1hr. The good barrier properties that were observed can be explained by the nano-sized grains along with the blocking effect of the impurities at the fast diffusion path of the grain boundaries. The transformation temperature from the amorphous to crystal structure is increased by doping the Re.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.771-780
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• 2001

It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

• Journal of Sensor Science and Technology
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• v.8 no.3
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• pp.283-290
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• 1999

The $n^+/p/p^+$ junction PERL solar cell of $0.1{\sim}2{\Omega}{\cdot}cm$ (100) p type silicon wafer was fabricated through the following steps; that is, wafer cutting, inverted pyramidally textured surfaces etching by KOH, phosphorus and boron diffusion, anti-reflection coating, grid formation and contact annealing. At this time, the optical characteristics of device surface and the efficiency of doping concentration for resistivity were investigated. And diffusion depth and doping concentration for n+ doping were simulated by silvaco program. Then their results were compared with measured results. Under the illumination of AM (air mass)1.5, $100\;mW/cm^2$ $I_{sc}$, $V_{oc}$, fill factor and the conversion efficiency were 43mA, 0.6 V, 0.62. and 16% respectively.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.9-15
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• 2021

Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (R_q) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.41-45
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• 2021

In this study, in order to secure the high reliability of the memristor, we adopted a patterned lithium filament seed layer as the main agent for resistive switching (RS) characteristic on the 30 nm thick ZrO₂ thin film at the device manufacturing stage. Lithium filament seed layer with a thickness of 5 nm and an area of 5 ㎛ × 5 ㎛ were formed on the ZrO₂ thin film, and various electrode areas were applied to investigate the effect of capacitance on filament type memristive behavior in the parallel memristive circuit of memristor and capacitor. The RS characteristics were measured in the samples before and after 250℃ post-annealing for lithium metal diffusion. In the case of conductive filaments formed by thermal diffusion (post-annealed sample), it was not available to control the filament by applying voltage, and the other hand, the as-deposited sample showed the reversible RS characteristics by the formation and rupture of filaments. Finally, via the comparison of the RS characteristics according to the electrode area, it was confirmed that capacitance is an important factor for the formation and rupture of filaments.

• Korean Journal of Materials Research
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• v.1 no.3
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• pp.125-131
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• 1991

Boron penetration phenomenon of $p^{+}$ silicon gate with as-deposited amorphous or polycrystalline Si upon high temperature annealing was investigated using high frequency C-V (Capacitance-Volt-age) analysis, CCST(Constant Current Stress Test), TEM(Transmission Electron Microscopy) and SIMS(Secondary Ion Mass Spectroscopy), C-V analysis showed that an as-deposited amorphous Si gate resulted in smaller positive shifts in flatband voltage compared wish a polycrystalline Si gate, thus giving 60-80 percent higher charge-to-breakdown of gate oxides. The reduced boron penetration of amorphous Si gate may be attributed to the fewer grain boundaries available for boron diffusion into the gate oxide and the shallower projected range of $BF_2$ implantation. The relation between electron trapping rate and flatband voltage shift was also discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.26-26
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• 2009

Vertically aligned arrays of mm-long multi-walled carbon nanotubes (MWCNTs) on Si substrates have been synthesized by water-assisted thermal chemical vapor deposition (CVD). The growth of CNTs was investigated by changing the experimental parameters such as growth temperature, growth time, gas composition, annealing time, catalyst thickness, and Al underlayer thickness. The 0.5-nm-thick Fe served as catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. We grew CNTs by adding a little amount of water vapor to enhance the activity and the lifetime of the catalyst. Al was very good at producing the nm-size catalyst particles by preventing "Ostwald ripening". The Al underlayer was varied over the range of 15~40 nm in thickness. The optimum conditions for the synthesis parameters were as follows: pressure of 95 torr, growth temperature of $815^{\circ}C$, growth for 30 min, 60 sccm Ar + 60 sccm $H_2$ + 20 sccm $C_2H_2$. The water vapor also had a great effect on the growth of CNTs. CNTs grew 5.03 mm long for 30 min with the water vapor added while CNTs were 1.73 mm long without water vapor at the same condition. As-grown CNTs were characterized by using scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM), and Raman spectroscopy. High-resolution transmission electron microscopy showed that the as-grown CNTs were of ~3 graphitic walls and ~6.6 nm in diameter.