• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.34 no.5
• /
• pp.314-320
• /
• 2021

Controlling ambient humid condition through high performance humidity sensors has become important for various fields, including industrial process, food storage, and the preservation of historic remains. Although aerosol deposited humidity sensors using ceramic BaTiO₃ (BT) material have been widely studied because of their longtime stability, there remain critical disadvantages, such as low sensitivity, low linearity, and slow response/recovery time in case of the sensors fabricated at room temperature. To achieve superior humidity sensing properties even at room temperature condition, BT-Cu composite films utilizing aerosol deposition (AD) process have been proposed based on the percolation theory. The BT-Cu composite films showed gradually improved sensing properties until the Cu concentration reached 15 wt% in the composite film. However, the excessive Cu (above 30 wt%) containing BT-Cu composite films showed a rapid decrease of the sensing properties. The results of observed surface morphology of the AD fabricated composite films, to figure out the metal filler effect, showed correlation between surface topography as well as size and the amount of open pores according to the metal filler content. Overall, it is very important not only dielectric constant of the humidity sensing films but also microstructures, because they affect either the variation range of capacitance by ambient humidity or adsorption/desorption of ambient humidity onto/from the humidity sensing films.

• Journal of IKEEE
• /
• v.26 no.3
• /
• pp.500-505
• /
• 2022

In this study, we designed oxide thin-film transistors (TFTs) with dual gate and tri layered split channels, and investigated the structural effect of the TFTs on the electrical characteristics. The dual gates played a key role in increasing the driving current, and the channel structure of tri layers and split form contributed to the increase in the carrier mobility. The tri layered channels consisting of the a-ITGZO and two ITO layers inserted between the gate dielectric and a-ITGZO led to the increase in the on-current by using ITO layers with high conductivity, and the split channels lowered series resistance of the channels. Compared with the mobility (15 cm²/V·s) of the single gate a-ITGZO TFT, the mobility (134 cm²/V·s) of the dual gate tri-layer split channel TFT was remarkably enhanced by the structural effect.

• Korean Journal of Materials Research
• /
• v.7 no.11
• /
• pp.969-973
• /
• 1997

저유전율 층간절연물질인 불소첨가 SiO$_{2}$박막을 ECR(electron cyclotron resonance) Plasma chemical vapor deposition 법으로 성막하였다. SiOF박막의 증착은 SiF$_{4}$/O$_{2}$의 가스유량비를 변수로하여 0.2에서 1.6까지 변화시켜 증착하였고, 이때 마이크로파 전력은 700W, 기판온도는 30$0^{\circ}C$에서 행하였다. 증착된 SiOF박막의 흡습특성을 알아보기 위하여 Fourier transformed infrared spectroscopy(FTIR)을 이용하여 분석한 결과, 가스유량비 (SiF$_{4}$O$_{2}$)가 0.2 에서 1.6으로 증가하였을 때 Si-Ostretching피크의 위치는 1072$cm^{-1}$ /에서 1088$cm^{-1}$ /로 증가하였으며, Si-F$_{2}$피크는 가스유량비가 1.0이상에서 나타나기 시작하였다. 또한 가스유량비가 0.2에서 0.8까지 변화하여 증착한 시편은 Si-OH 피크가 관찰되지 않았지만 가스유량비가 1.0이상(11.8at.% F함유)의 시편의 경우 Si-OH 피크가 관찰되어 내흡습성이 저하되고 있음을 확인할 수 있었다.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
• /
• 2002.10b
• /
• pp.441-442
• /
• 2002

Chemical mechanical polishing (CMP) is a manufacturing process that uses controlled wear to planarize dielectric and metallic layers on silicon wafers. CMP experiments revealed that a sub-ambient film pressure developed at the wafer/pad interface. Additionally, dishing occurs in CMP processes when the copper-in-trench lines are removed at a rate higher than the barrier layer. In order to study dishing across a stationary wafer during polishing, dishing maps were created. Since dishing is a function of the total contact pressure resulting from the applied load and the fluid pressure, the hydrodynamic pressure model was refined and used in an existing model to study copper dishing. Density maps, highlighting varying levels of dishing across the wafer face at different radial positions, were developed. This work will present the results.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.247-247
• /
• 2012

Plasmon subwavelength nanostructures enable the structurally modulated color due to the resonance conditions for the specific wavelength range of light with the nanoscale hole arrays on a metal layer. While the unique properties offered from a single layer of metal may open up the potential applications of integrated devices to displays and sensors, fabrication requirements in nanoscale, typically on the order of or smaller than the wavelength of light in a corresponding medium can limit the cost-effective implementation of the plasmonic nanostructures. Simpler nanoscale replication technologies based on the soft lithography or roll-to-roll nanoimprinting can introduce economically feasible manufacturing process for these devices. Such replication requires an optimal design of a master template to produce a stamp that can be applied for a roll-to-roll nanoimprinting. In this paper, a master mold with subwavelength nanostructures is fabricated and optimized using focused ion beam for the applications to nanoimprinting process. Au thin film layer is deposited by sputtering on a glass that serves as a dielectric substrate. Focused ion beam milling (FIB, JEOL JIB-4601F) is used to fabricate surface plasmon subwavelength nanostructures made of periodic hole arrays. The light spectrum of the fabricated nanostructures is characterized by using UV-Vis-NIR spectrophotometer (Agilent, Cary 5000) and the surface morphology is measured by using atomic force microscope (AFM, Park System XE-100) and scanning electron microscope (SEM, JEOL JSM-7100F). Relationship between the parameters of the hole arrays and the corresponding spectral characteristics and their potential applications are also discussed.

• Korean Journal of Materials Research
• /
• v.19 no.11
• /
• pp.625-630
• /
• 2009

Embedding of active devices in a printed circuit board has increasingly been adopted as a future electronic technology due to its promotion of high density, high speed and high performance. One responsible technology is to embedded active device into a dielectric substrate with a build-up process, for example a chipin-substrate (CiS) structure. In this study, desmear treatment was performed before Cu metallization on an FR-4 surface in order to improve interfacial adhesion between electroless-plated Cu and FR-4 substrate in Cu via structures in CiS systems. Surface analyses using atomic force microscopy and x-ray photoemission spectroscopy were systematically performed to understand the fundamental adhesion mechanism; results were correlated with peel strength measured by a 90o peel test. Interfacial bonding mechanism between electrolessplated Cu and FR-4 substrate seems to be dominated by a chemical bonding effect resulting from the selective activation of chemical bonding between carbon and oxygen through a rearrangement of C-C bonding rather than from a mechanical interlocking effect. In fact, desmear wet treatment could result in extensive degradation of FR-4 cohesive strength when compared to dry surface-treated Cu/FR-4 structures.

• Electrical & Electronic Materials
• /
• v.16 no.9
• /
• pp.63.1-63
• /
• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• Electrical & Electronic Materials
• /
• v.10 no.5
• /
• pp.473-480
• /
• 1997

Surface passivation using glass powders results in good reliability for high voltage silicon power devices. In this paper Zinc borosilicate glass and Lead borosilicate glass were prepared for the purpose of passivating, and a deposition technique of glass films on the silicon surface by electrophoresis in which acetone is used as a suspension medium has been investigated. Their physical properties were compared using DTA, SEM, XRD, as a function of firing temperature, I can get the fine films of 22${\mu}{\textrm}{m}$ thickness with Lead borosilicate glass under 300 volts applied, 3 minutes and $700^{\circ}C$ firing temperature. Also I can get the fine films of 17${\mu}{\textrm}{m}$ thickness with Zinc borosilicate glass under same conditions. As a result of investigation of glass films from which glass layer was removed by placing it in HCl, it has been found that pre-firing and annealing play an important role to achieve uniform and fine glass deposition films. And also it was found that relative dielectric constant is independence of frequency.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.3 s.32
• /
• pp.63-70
• /
• 2004

The structural, electrical properties of $(Ba, Sr)TiO_3[BSTO]/RuO_2$ thin films were examined by the addition of amorphous BSTO layer between crystlline BSTO film and $RuO_2$ substrate. We prepared BSTO films with double-layered structure, that is, amorphous layers deposited at $60^{\circ}C$ and crystalline films. Crystalline films were prepared at 550 on amorphous BSTO layer. The thickness of the amorphous layers was varied from 0 to 170 nm. During the deposition of crystalline films, the crystallization of the amorphous layers occurred and the structure was changed to circular while crystalline BSTO films showed columnar structure. Due to insufficient annealing effect, amorphous BSTO phase was observed when the thickness of the amorphous layers exceeded 30 nm. Amorphous BSTO layer could also prevent the formation of oxygen deficient region in $RuO_2$ surface. Leakage current of total BSTO films decreased with increasing amorphous layer thickness due to structural modifications. Dielectric constant showed maxi-mum value of 343 when amorphous layer thickness was 30 nm at which the improvement by grain growth and the degradation by amorphous phase were balanced.

• The Korean Journal of Ceramics
• /
• v.1 no.1
• /
• pp.7-12
• /
• 1995

When a $Ta_O_5$ dielectric film is deposited on a bare silicon, the growth of $SiO_2$ at the $Ta_O_5$/Si interface cannot be avoided. Even though the $SiO_2$ layer is ultrathin (a few nm), it has great effects on the electrical properties of the capacitor. The concentration depth profiles of the ultrathin interfacial $SiO_2$ and $SiO_2/Si_3N_4$ layers were obtained using an Auger electron spectroscopy (AES) equipped with a cylindrical mirror analyzer (CMA). These AES depth profiles were quantitatively analyzed by comparing with the theoretical depth profiles which were obtained by considering the inelastic mean free path of Auger electrons and the angular acceptance function of CMA. The direct measurement of the interfacial layer thicknesses by using a high resolution cross-sectional TEM confirmed the accuracy of the AES depth analysis. The $SiO_2/Si_3N_4$ double layers, which were not distinguishable from each other under the TEM observation, could be effectively analyzed by the AES depth profiling technique.