• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.158-163
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• 1996

In the conventional GaAs MESFET circuit simulation, the DC and transient simulation results are often failed due to the discontrinuities of the first and second order derivatives arising from the use of separate C-V models in linear, satruration, and transition regions. In this paper, we propose a unified capacitance model for linear, transition, and saturation regions by using a unified channel length modulation effect that is derived by extending the channel length modulation effect in the saturation region to the linear region. Calculated resutls from the proposed capacitance model agree well with 2-D device simulation resutls. Thus, the proposed model is expected to be useful in circuit simulation.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.311-315
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• 2009

2-dimensional (2D) dopant profiling in semiconductor device was carried out by electron holography and scanning capacitance microscopy methods with the same multi-layered p-n junction sample. The dopant profiles obtained from two methods are in good agreement with each other. It demonstrates that reliability of dopant profile measurement can be increased through precise comparison of 2D profiles obtained from various techniques.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.172-180
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• 2003

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.181-184
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• 1999

This paper presents the accurate deembeding method for pad and parasitics of MOSFET device. rad effects are deembedded using THRU LINE, which is much simpler method without laborious fitting procedure compared with conventional OPEN and SHORT pad modeling. Parasitic resistance extraction uses the algebraic relation between increments of inversion layer charge and oxide capacitance. It is especially adequate for insulating gate junction device. Extracted parasitics are verified through comparing modeled and measured S parameters.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1797-1799
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• 1999

In this paper, to implement the electrical equivalent modeling of powder electroluminescent device, capacitate equation of device was chosen. The conventional structure device which have dielectric and phosphor layer between electrodes, and the single emission structure device which means that dielectric and phosphor were mixed between electrodes, were investigated. As a result, It was possible to make the equation that is transferred capacitance to phosphor layer, and using measured brightness efficiency and conductivity of devices was calculated.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.290-294
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• 2000

ZnS:Mn TFEL devices were fabricated by electron-beam evaporation method and then the electro-optical properties were investigated. To investigate the capacitance which was due to oxygen vacancy at the $Ta_2O_5$ thin film, AES(Auger Electron Spectroscopy) and C-F(capacitance-frequency) measurements were used. It was found that the capacitance was decreased by annealing the $Ta_2O_5$ film in oxygen ambience. From EL emission measurement, we observed the EL emission spectrum which had the peak range from 550nm and 650nm. This emission is associated with the transition from $^4T_1(^4G)$ first excited state to $^6A_1(^6S)$ ground state in the $3d^5$ energy level configuration of $Mn^{2+}$ occurs. The threshold voltage of EL device with $Ta_2O_5$ insulator layer was found to be 24V~28V. The CIE color coordinates of these emission are X=0.5151, Y=0.4202 which is yellowish orange emitting. The EL device using $Ta_2O_5$ insulator layer can be driven with a low voltage which is beneficial to the practical application.

• Journal of the Korea Organic Resources Recycling Association
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• v.30 no.2
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• pp.5-15
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• 2022

In this study, heated tobacco biomass was prepared as an active material for supercapacitor device. Retrieved tobacco leaf from the heated tobacco was carbonized at various temperature(800/850/950℃). Carbonized tobacco leaf material synthesized at 850℃ exhibited the highest C/O ratio, indicating the finest carbon quality. In addition, polypyrrole was coated onto the carbonized leaf material for increasing the electrochemical performance via low-temperature polymerization method. As-synthesized carbonized leaf material at 850℃(CTL-850)-based electrode and polypyrrole-coated carbonized leaf material(CTL-850/PPy)-based electrode displayed outstanding specific capacitances of 100.2 and 155.3F g^-1 at 1 A g^-1 with opertaing window of -1.0V and 1.0V. Asymmetric supercapacitor device, assembled with CTL-850 as the negative electrode and CTL-850/PPy as the positive electrode, manifested specific capacitance of 31.1F g^-1(@1 A g^-1) with widened operating voltage window of 2.0V. Moreover, as-prepared asymmetric supercapacitor device was able to lighten up the RED Led (1.8V), suggesting the high capacitance and extension of operating voltage window. The result of this research may help to pave the new possibility toward preparing the effective energy storage device material recycling the biomass.