• 제목/요약/키워드: description logic

검색결과 166건 처리시간 0.024초

A Description of English Relative Clauses With conceptual Structure Theory (개념구조론에 의한 영어 관계절의 기술)

  • KihoCho
    • Korean Journal of Cognitive Science
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    • 제4권2호
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    • pp.29-51
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    • 1994
  • This paper presents a new approach to describing the meanings of English relative clauses with the theoretical framework of Conceptual Structure Theory (henceforth CST)which builds on the pionerring work of Sowa.And this paper aims at proposing some extensions to his work. CST describes the conceptual structrures of sentences with conceptual graphs(henceforth CG). which have begun to be used as an intermediate language in natural language processing and machine translation of computer.CGs are composed of concept types and conceptual relation types. They are a system of logic for semantic representation of sentences. This paper focuses on showing the differences of the CGs according to the functions of English relative clauses. English relative clauses are divided into restrictive and nonrestrictive uses.And this paper describes a restrictive clause with a CG including a expression.which derives from the viewpoint of Montague-semantics and Nom-S Analysis.This paper deals mainly with the relative clauses of double restroction as an example of restrictive relative clauses.The description of a nonrestrictive relative clause does not need any-expression, for it doesn's involve the meaning of set.And this paper links the CG of an appositive relative clause,which is a kind of nonrestrictive clauses,to the concept of the antecedent in the main clause.The description of a nonrestrictive relative clause with adverbial meaning is strated with two CGs for the main clause and the relative clause.They are linked with an appropriate intersentential conceptual relation type according to the contextual realtions between them.This paper also presents a CG of a sentential relative clause,which gives a comment on the main clause.

Filed Programmable Logic Control and Test Pattern Generation for IoT Multiple Object switch Control (사물인터넷 환경에서 다중 객체 스위치 제어를 위한 프로그래밍 가능한 로직제어 및 테스트 패턴 형성)

  • Kim, Eung-Ju;Jung, Ji-Hak
    • Journal of Internet of Things and Convergence
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    • 제6권1호
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    • pp.97-102
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    • 2020
  • Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis (신호전이그래프에 기반한 비동기식 논리합성의 고유한 특성을 고려한 신호전이그래프의 자동생성)

  • Kim, Eui-Seok;Lee, Jeong-Gun;Lee, Dong-Ik
    • The KIPS Transactions:PartA
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    • 제9A권3호
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    • pp.351-362
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    • 2002
  • Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

Design and Qualification of FPGA-based Controller applying HPD Development Life-Cycle for Nuclear Instrumentation and Control System (HPD 개발수명주기를 적용한 원전 FPGA 기반 제어기의 설계와 검증)

  • Lee, Joon-Ku;Jeong, Kwang-Il;Park, Geun-Ok;Sohn, Kwang-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • 제9권6호
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    • pp.681-687
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    • 2014
  • Nuclear industries have faced unfavorable circumstances such as an obsolescence of the instrumentation and control system, and therefore nuclear society is striving to resolve this issue fundamentally. IEC and IAEA judge that FPGA technology is a good replacement for Programmable Logic Controller (PLC) of Nuclear Instrumentation and Control System. FPGAs are currently highlighted as an alternative means for obsolete control systems. Because the main function inside an FPGA is initially developed as software, good software quality can impact the reliability of an FPGA-based controller. Therefore, it is necessary to establish a software development aspect strategy that enhances the reliability of an FPGA-based controller. In terms of software development, HDL-Programmed Device (HPD) Development Life Cycle is applied into FPGA-based Controller. The burn-in test and environmental(temperature) test should be performed in order to apply into nuclear instrumentation and control system. Therefore it is ensured that the developed FPGA-based controller are normally operated for 352 hours and 92 hours in test chamber of Korea Institute of Machinery and Materials (KIMM).

Using Description Logic and Rule Language for Web Ontology Modeling (서술논리와 규칙언어를 이용한 웹 온톨로지 모델링)

  • Kim, Su-Gyeong
    • Proceedings of the Korea Inteligent Information System Society Conference
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    • 한국지능정보시스템학회 2007년도 한국지능정보시스템학회
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    • pp.277-285
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    • 2007
  • 본 연구는 시맨틱웹 응용의 중심 기술인 웹 온톨로지의 표현과 추론을 위해 서술 논리와 규칙언어를 기반으로하는 웹 온톨로지 모델링 방법을 제안한다. 현재 웹 온톨로지 표현 언어인 OWL DL은 서술 논리에 근거하여 표현되는 것이나, 기계나 온톨로지 공학자가 OWL로 기술된 온톨로지를 직관적으로 이해하고 공유할 수 있는 형식적이고 명시적인 온톨로지의 지식 표현은 부족한 실정이다. 따라서 본 연구는 시맨틱웹이 목적하는 웹 온톨로지 구축을 위한 웹 온톨로지 모델링 방법으로 웹 온톨로지 모델링 계층을 제안하고, 제안된 각 계층에 따라 서술 논리의 TBox와 ABox의 구조와 SWRL을 기반으로 지식을 표현하는 웹 온톨로지 모델링 방법을 제안한다. 제안된 웹 온톨로지 모델링 방법의 성능 검증을 위해 제안 방법에 따라 웹 온톨로지를 구축하였고, SPARQL과 TopBraid의 DL Inference를 이용하여 구축된 웹 온톨로지의 성능을 검증하였다.

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Development of Combustion Model for Engine Control Algorithm Design (엔진제어 알고리즘 설계를 위한 연소모델 개발)

  • Park, Young-Kug
    • Transactions of the Korean Society of Automotive Engineers
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    • 제18권3호
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    • pp.26-36
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    • 2010
  • This paper provides a description of the combustion model to obtain an accurate dynamic engine phenomena that satisfies real-time simulation for model-based engine control. The combustion chamber is modeled as a storage device for mass and energy. The combustion process is modeled in terms of a two-zone model for the burned and unburned gas fractions. The mass fraction burnt is modeled in terms of a Wiebe function. The instantaneous net engine torque is calculated from the engine speed and the instantaneous piston work. The modeling accuracy has been tested with a cylinder pressure data on a test bench and also the ability of real-time simulation has been checked. The results show that combustion model yields sufficiently good performance for the model-based control logic design. However the influence factors effected on model accuracy are some room for improvement.

Efficient Rule-based OWL Reasoning by Combing Meta Rules and Translation (메타 규칙과 번역의 혼용을 통한 규칙엔진 기반 OWL 추론 엔진의 성능 향상 방법)

  • Jang, Min-Su;Sohn, Joo-Chan;Cho, Young-Jo
    • Proceedings of the Korean Information Science Society Conference
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    • 한국정보과학회 2007년도 한국컴퓨터종합학술대회논문집 Vol.34 No.1 (D)
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    • pp.214-219
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    • 2007
  • 생성 규칙(Production Rule)과 이를 기반으로 하는 규칙 엔진(Rule Engine)을 기반으로 한 OWL 추론 엔진은 메타 규칙((Meta Rule)에 의존해 왔다. 메타 규칙은 OWL의 의미론 (Semantics)을 표현하기 용이하여 보다 손쉽게 OWL 추론 엔진을 구현할 수 있다는 장점을 제공하였으나 OWL 추론 성능에 있어 추론 속도와 대용량 온톨로지 처리 측면에서 모두 만족할 만한 성과를 얻지 못하였다. 본 논문은 DLP(Description Logic Programming)의 번역 접근법을 기반으로 한 번역 규칙(Translation Rules)을 메타 규칙과 혼용하는 OWL 추론 기법을 소개한다. LUBM 벤치마크를 통해 이 기법이 메타 규칙만을 이용했을 때 보다 100% 이상 추론 성능을 향상시켰을 뿐 아니라 메모리 사용량도 대폭 축소시켰음을 확인할 수 있었다. 또한, 번역을 통해 제한없는 차수 제약(Cardinality Restriction) 관련 추론을 지원하는 등 보다 넓은 범위의 OWL 추론을 지원할 수 있다.

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State Assignment Method for Control Part Implementation of Effective-Area (효율적인 면적의 제어부 실현을 위한 상태 할당 방법)

  • Park, S.K.;Choi, S.J.;Cho, J.W.;Jong, C.W.;Lim, I.C.
    • Proceedings of the KIEE Conference
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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    • pp.1556-1559
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    • 1987
  • In this paper, a new state assignment method is proposed for the implementation of the area-effective control part. Introducing the, concept of adjacency matrix to control table generated by SDL(Symbolic Description Language) hardware compiler, a state assignment method is proposed with which minimal number of flip flops and effective number of product terms can be obtained to accomplish the area-effective implementation. Also, with substituting the assigned code to state transition table, boolean equations are obtained through 2-level logic minimization. Proposed algorithm is programmed in C-language on VAX-750/UNIX and b efficiency is shown by the practical example.

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VHDL Implementation of an LPC Analysis Algorithm (LPC 분석 알고리즘의 VHDL 구현)

  • 선우명훈;조위덕
    • Journal of the Korean Institute of Telematics and Electronics B
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    • 제32B권1호
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    • pp.96-102
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    • 1995
  • This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

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EOL : Epistemological Ontology Language and Reasoner with SUNHI for Ubiquitous Computing Environment (EOL : SUNHI 표현범위를 가진 인식론적 온톨로지 표현 언어 와 추론엔진)

  • Ma, Jong-Soo;Kim, Min-Soo;Kim, Min-Koo
    • 한국HCI학회:학술대회논문집
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    • 한국HCI학회 2007년도 학술대회 1부
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    • pp.835-840
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    • 2007
  • 현재 이슈가 되고 있는 유비쿼터스 컴퓨팅 환경에서 서비스를 제공함에 있어 사용자의 만족도를 높여주기 위해 서비스의 지능화가 필요하다. 이러한 지능적인 서비스를 제공하기 위해 서비스에 필요한 지식을 논리적으로 표현하고, 체계적으로 추론할 수 있는 방법이 요구된다. 이를 위해 표현 범위가 넓고 유연한 일차 술어 논리(FOL)는 여러 분야에서 사용되었으며, 추론 시스템에 이용되고 있다. 그러나 풍부한 표현 범위는 유비쿼터스 컴퓨팅 환경에서의 오브젝트 관리에 있어 많은 계산비용이 소요된다. 서비스의 빠른 제공을 목표로 하고 있는 유비쿼터스 환경에서 이러한 계산비용은 서비스 제공 시간을 늦추는 요인이 된다. 이러한 문제를 극복하고 지식의 의미를 부여하는 방법으로 Description Logic과 온톨로지가 연구되고 있다. 특히 OWL(Web Ontology Language)은 풍부한 표현력을 제공하고 있으며, W3C에 의해 온톨로지 기술의 표준으로 제안되었다. 그러나 풍부한 표현 범위는 실제 컴퓨팅 환경에서 모두 사용되지 않고, 기술 및 추론의 복잡함으로 overhead가 발생한다. 본 논문에서는 이를 극복하고자 실제 유비쿼터스 환경에서 요구되는 표현 범위를 만족하는 SUNHI의 표현력을 갖는 EOL을 제안한다.

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