• Title/Summary/Keyword: description logic

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Low Power Symbol Detector for MIMO Communication Systems (MIMO 통신 시스템을 위한 저전력 심볼 검출기 설계 연구)

  • Hwang, You-Sun;Jang, Soo-Hyun;Jung, Yun-Ho
    • Journal of Advanced Navigation Technology
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    • v.14 no.2
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    • pp.220-226
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    • 2010
  • In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

Embodiment of PWM converter by using the VHDL (VHDL을 이용한 PWM 컨버터의 구현)

  • Baek, Kong-Hyun;Joo, Hyung-Jun;Lee, Hyo-Sung;Lim, Yong-Kon;Lee, Heung-Ho
    • Proceedings of the KIEE Conference
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    • 2002.11d
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    • pp.197-199
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    • 2002
  • The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

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Adaptive Software Framework based on Acquiring Context Information using Plane Image Processing (평면 영상 분석을 통한 상황 정보 획득 기반의 적응형 소프트웨어 프레임워크)

  • Kim, Ki-Mun;Jung, Woo-Sung;Lee, Byung-Jeong;Wu, Chi-Su
    • Journal of KIISE:Software and Applications
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    • v.34 no.8
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    • pp.763-771
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    • 2007
  • As software is widely used on various environments today, there is an increasing need for adaptive software. Adaptive software is robust and flexible software that modifies its own behavior in response to the changes in its environment. Due to time constraints, high complexity and so on, it is hard to acquire context information from environment. So, when implementing software, it is common to think easily acquired data to be the environments. This research proposes an adaptive software framework that assumes plane images to be environments. Plane images are easy to acquire and have enough complexity. From this, our framework is able to acquire context information, reasons with action rule, and acts on the result of reasoning. Stand on this framework, implements software that plays a simple game automatically.

Integration of OWL and SWRL Inference using Jess (Jess를 이용한 OWL과 SWRL의 통합추론에 관한 연구)

  • Lee Ki-Chul;Lee Jee-Hyong
    • Journal of the Korean Institute of Intelligent Systems
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    • v.15 no.7
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    • pp.875-880
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    • 2005
  • OWL(Web Ontology Language) is the Ontology Standard Language and the a lot of Ontologies are being constructed in OWL. But the research on the extension of OWL is also progressing because of the limit of representation power of in OWL language. The W3C suggests the SWRL(Semantic Web Rule Language) based on the combination of OWL and RuleML(Rule Markup Language), which is improved in the representation of rule. Thus, both OWL and SWRL are used for developing ontologies. However, research on inference of ontologies written in both languages is just begun. These day, for the inference of ontologies written in both languages, ontologies and divided in to two parts. The part written in OWL and written in SWRL. For the inference of the part written in OWL, Racer, a DL based inference engine, is used and for the other part Jess, a rule-based engine, is used. In this paper, we will propose three methods for integrated inference of the OWL part and the SWRL part of ontologies using Jess and some tools for ontology inference : OWLJessKB and SWRL Factory

Development and Application of Process Model for Description of Load Change of Boiler Plant in High Load (고부하에서의 보일러 플랜트 부하변동 묘사를 위한 프로세스 모델 개발 및 적용)

  • Park, Jeong;Lee, Ki-Hyun;Yang, Li-Ming;In, Jong-Soo;Park, Seok-Ho;Kweon, Sang-Hyeok;Oh, Dong-Han
    • Journal of Energy Engineering
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    • v.6 no.1
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    • pp.41-51
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    • 1997
  • A dynamic mathematical model of a thermal power plant with a single drum-type boiler is described with the base on modular concept. The present process model, which is including full scope of the components and high load changes, is based on physical approach through lumped parameters. The module, which means a component of the power plant and must essentially depict the characteristics of the component well, might be interconnected using pressure nodal method in a arrangement determined by users. With the results of the load changes of 75 MW to 95 MW and 95MW to 75 MW with the rate of 3 MW/min, the applicability of the process model is examined connecting to DCS(Dispersion Control System), which has a real running logic of 100 MW real power plant.

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Ontology and Sequential Rule Based Streaming Media Event Recognition (온톨로지 및 순서 규칙 기반 대용량 스트리밍 미디어 이벤트 인지)

  • Soh, Chi-Seung;Park, Hyun-Kyu;Park, Young-Tack
    • Journal of KIISE
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    • v.43 no.4
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    • pp.470-479
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    • 2016
  • As the number of various types of media data such as UCC (User Created Contents) increases, research is actively being carried out in many different fields so as to provide meaningful media services. Amidst these studies, a semantic web-based media classification approach has been proposed; however, it encounters some limitations in video classification because of its underlying ontology derived from meta-information such as video tag and title. In this paper, we define recognized objects in a video and activity that is composed of video objects in a shot, and introduce a reasoning approach based on description logic. We define sequential rules for a sequence of shots in a video and describe how to classify it. For processing the large amount of increasing media data, we utilize Spark streaming, and a distributed in-memory big data processing framework, and describe how to classify media data in parallel. To evaluate the efficiency of the proposed approach, we conducted an experiment using a large amount of media ontology extracted from Youtube videos.

VLSI Design of H.264/AVC CAVLC encoder for HDTV Application (실시간 HD급 영상 처리를 위한 H.264/AVC CAVLC 부호화기의 하드웨어 구조 설계)

  • Woo, Jang-Uk;Lee, Won-Jae;Kim, Jae-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.45-53
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    • 2007
  • In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

Development of Chip-based Precision Motion Controller

  • Cho, Jung-Uk;Jeon, Jae-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1022-1027
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    • 2003
  • The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

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Implementation of WLAN Baseband Processor Based on Space-Frequency OFDM Transmit Diversity Scheme (공간-주파수 OFDM 전송 다이버시티 기법 기반 무선 LAN 기저대역 프로세서의 구현)

  • Jung Yunho;Noh Seungpyo;Yoon Hongil;Kim Jaeseok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.5 s.335
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    • pp.55-62
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    • 2005
  • In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

A Study on the User Experience according to the Method and Detail of Recommendation Agent's Explanation Facilities (추천 에이전트의 설명 방식과 상세도에 따른 사용자 경험 차이에 관한 연구)

  • Kang, Chan-Young;Kim, Hyek;Kang, Hyun-Min
    • The Journal of the Korea Contents Association
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    • v.20 no.8
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    • pp.653-665
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    • 2020
  • As the use of recommended agents has become more active, the "Explain Facilities" is drawing attention as a way to solve the black-box problem that could not explain internal logic to users. This study wants to look at how the description Method and Detail affects to user experience. The Explanation method was divided into 'why the agent did a particular action' and 'why not do a particular action' and the detail condition were divided into 'high or low'. Studies have found that 'why method' have a positive effect on users' transparency, trust, satisfaction, and behavioral intention to use, and 'high detail condition' higher the user' Psychological reactance. In addition, it was found that the explanation methods and detail influenced the 'Explanation' perception through interaction and tended to affect satisfaction and intention to adopt recommendation. This study suggested that careful attention is needed to determine the method and detail of the Explanation facilities in the context of the recommended agent, based on the research findings that it affects the user experience through the interaction of the method and detail.