• Journal of KIISE
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• v.45 no.2
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• pp.113-125
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• 2018

Recently, with the advent of the Big Data era, we have gained the capability of acquiring vast amounts of knowledge from various fields. The collected knowledge is expressed by well-formed formula and in particular, OWL, a standard language of ontology, is a typical form of well-formed formula. The symbolic reasoning is actively being studied using large amounts of ontology data for extracting intrinsic information. However, most studies of this reasoning support the restricted rule expression based on Description Logic and they have limited applicability to the real world. Moreover, knowledge management for inaccurate information is required, since knowledge inferred from the wrong information will also generate more incorrect information based on the dependencies between the inference rules. Therefore, this paper suggests that the SWAT, knowledge management system should be combined with the SWRL (Semantic Web Rule Language) reasoning based on ATMS (Assumption-based Truth Maintenance System). Moreover, this system was constructed by combining with SWRL reasoning and ATMS for managing large ontology data based on the distributed In-memory framework. Based on this, the ATMS monitoring system allows users to easily detect and correct wrong knowledge. We used the LUBM (Lehigh University Benchmark) dataset for evaluating the suggested method which is managing the knowledge through the retraction of the wrong SWRL inference data on large data.

• Korean Journal of Logic
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• v.18 no.2
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• pp.217-241
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• 2015

Brandom upholds the anaphoric theory of reference. On this theory, reference is a relation of anaphoric dependence between linguistic items rather than a substantial relation between linguistic items and non-linguistic objects. In addition, 'refers' is a pronoun-forming operator, which is used to form anaphorically indirect descriptions such as 'the one referred to as "Leibniz"'. Recently, Arbid $B{\aa}ve$ raises three objections against this theory. First, the anaphoric theory distinguishes between ordinary descriptions and anaphorically indirect descriptions in terms of iterability. But this condition is not an adequate ground for asserting that anaphorically indirect descriptions form a distinctive semantic category. Second, sentences containing a pronoun such as 'he' and sentences containing an anaphorically indirect description such as 'the one referred to as "Leibniz"' have different modal statuses. Consequently, indirect descriptions are semantically different from paradigmatic anaphors. Third, on the anaphoric theory, expressions of the form 'a' and the corresponding indirect descriptions of the form 'the one referred to as "a"' are intersubstitutable. But we can make an equivalent claim by using the more general semantic concepts such as equivalence and intersubstitutability, instead of using notions such as 'anaphor' and 'antecedent'. So the anaphoric theory is explanatorily idle. In this paper I argue that these objections do not pose a serious problem for the anaphoric theory of reference. I argue thereby that the anaphoric theory of reference is a promising theory which provides us with the right understanding of the expression 'refers'.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.40 no.5
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• pp.429-437
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• 2022

Recently, the demand for a QA (Question Answering) system for human-machine communication has increased. Among the QA systems, a closed domain QA system that can handle spatial-related questions is called GeoQA. In this study, a new type of graph database, LPG (Labeled Property Graph) was used to overcome the limitations of the RDF (Resource Description Framework) based database, which was mainly used in the GeoQA field. In addition, GraphQL (Graph Query Language), an API-type query language, is introduced to address the fact that the LPG query language is not standardized and the GeoQA system may depend on specific products. In this study, database was built so that answers could be retrieved when spatial-related questions were entered. Each data was obtained from the national spatial information portal and local data open service. The spatial relationships between each spatial objects were calculated in advance and stored in edge form. The user's questions were first converted to GraphQL through FOL (First Order Logic) format and delivered to the database through the GraphQL server. The LPG used in the experiment is Neo4j, the graph database that currently has the highest market share, and some of the built-in functions and QGIS were used for spatial calculations. As a result of building the system, it was confirmed that the user's question could be transformed, processed through the Apollo GraphQL server, and an appropriate answer could be obtained from the database.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.429-435
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• 2018

In radar systems, FFT (fast Fourier transform) operation is necessary to obtain the range and velocity of target, and the design of an FFT processor which operates at high speed is required for real-time implementation. The perfect shuffle network is suitable for high-speed FFT processor. In particular, twice perfect shuffle network based on radix-4 is preferred for very high-speed FFT processor. Moreover, radar systems that requires various velocity resolution should support scalable FFT points. In this paper, we propose a 8~1024-point scalable FFT processor based on twice perfect shuffle network algorithm and present hardware design and implementation results. The proposed FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using $0.65{\mu}m$ CMOS process. It is confirmed that the proposed processor includes logic gates of 3,293K.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.4
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• pp.286-290
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• 2005

We consider the poisson equation where the functions involved are periodic including the solution function. Let $R=[0,1]{\times}[0,l]{\times}[0,1]$ be the region of interest and let $\phi$(x,y,z) be an arbitrary periodic function defined in the region R such that $\phi$(x,y,z) satisfies $\phi$(x+1, y, z)=$\phi$(x, y+1, z)=$\phi$(x, y, z+1)=$\phi$(x,y,z) for all x,y,z. We describe a very simple method for solving the equation ${\nabla}^2u(x, y, z)$ = $\phi$(x, y, z) based on the cubic spline interpolation of u(x, y, z); using the requirement that each interval [0,1] is a multiple of the period in the corresponding coordinates, the Laplacian operator applied to the cubic spline interpolation of u(x, y, z) can be replaced by a square matrix. The solution can then be computed simply by multiplying $\phi$(x, y, z) by the inverse of this matrix. A description on how the storage of nearly a Giga byte for $20{\times}20{\times}20$ nodes, equivalent to a $8000{\times}8000$ matrix is handled by using the fuzzy rule table method and a description on how the shape preserving property of the Laplacian operator will be affected by this approximation are included.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.41-50
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• 2010

In this paper, an area-efficient symbol detector is proposed for MIMO communication systems with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing mode and spatial diversity mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate，the complexity of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of logic slices for the proposed symbol detection is 52490 and the number of DSP48s (dedicated multiplier) is 52, which are reduced by 35.3% and 85.3%, respectively, compared with the conventional architecture.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.634-643
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• 1999

This paper concerns an implementation of f~rry logic controller (FLC') on a reconfigurahle FP