• Title/Summary/Keyword: delay fault

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A Study on DC Offset Removal using Low-Pass Filter in AT Feeder System for Electric Railway (전기철도 AT급전계통에 Low-Pass Filter를 이용한 직류옵셋 제거에 관한 연구)

  • Lee, Hwan;Jung, No-Geon;Kim, Jae-Moon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.6
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    • pp.1108-1114
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    • 2016
  • The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

Development of Delta-I ground fault Protective Relaying Scheme for DC Traction Power Supply System (비접지 DC 급전시스템에서의 Delta-I 지락보호계전 시스템)

  • Chung, Sang-Gi;Kwon, Sam-Young;Jung, Ho-Sung;Kim, Ju-Rak
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.55 no.12
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    • pp.529-535
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    • 2006
  • In DC tracking power supply system, ground faults are currently detected by the potential relay, 64P. Though 64P relay detects ground fault, it cannot identify the faulted region which causes long traffic delays and safety problem to passengers. A new ground fault protective relay scheme, ${\Delta}I$ ground fault protective relay, that can identify the faulted region is presented in this paper. In ${\Delta}I$ ground fault protective relaying scheme, ground fault is detected by 59, overvoltage relay, which operates ground switch installed between the negative bus and the ground. It preliminarily chooses the faulted feeder after comparing the current increases among feeders and trips the corresponding feeder breaker. After some time delay, it then recloses the breaker if it finds the preselected feeder is not the actual faulted feeder. Whether or not the preselected feeder is the actual faulted feeder is determined by checking the breaker trip status in the neighboring substation in the direction of the tripped breaker. If the corresponding breaker in the neighboring substation is also tripped, it finally judges the preselected feeder is actually a faulted feeder. Otherwise it recloses the tripped breaker. Its algorithms is presented and verified by EMTP simulation.

Incipient Fault Detection of Reactive Ion Etching Process

  • Hong, Sang-Jeen;Park, Jae-Hyun;Han, Seung-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.6 no.6
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    • pp.262-271
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    • 2005
  • In order to achieve timely and accurate fault detection of plasma etching process, neural network based time series modeling has been applied to reactive ion etching (RIE) using two different in-situ plasma-monitoring sensors called optical emission spectroscopy (OES) and residual gas analyzer (RGA). Four different subsystems of RIE (such as RF power, chamber pressure, and two gas flows) were considered as potential sources of fault, and multiple degrees of faults were tested. OES and RGA data were simultaneously collected while the etching of benzocyclobutene (BCB) in a $SF_6/O_2$ plasma was taking place. To simulate established TSNNs as incipient fault detectors, each TSNN was trained to learn the parameters at t, t+T, ... , and t+4T. This prediction scheme could effectively compensate run-time-delay (RTD) caused by data preprocessing and computation. Satisfying results are presented in this paper, and it turned out that OES is more sensitive to RF power and RGA is to chamber pressure and gas flows. Therefore, the combination of these two sensors is recommended for better fault detection, and they show a potential to the applications of not only incipient fault detection but also incipient real-time diagnosis.

A Method for Fault detecting on Power Transmission Network by use of M-sequence Correlation

  • Nishiyama, Eiji;Kuwanami, Kenshi;Owaki, Kosuke
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2570-2575
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    • 2003
  • Monitoring a power transmission line is significant for power electric companies. In this paper, we propose a new method for detecting an fault point of power transmission line by use of M-sequence correlation technique. In this method, detecting signal is used as one or plural M-sequences ( same characteristic polynomial, including normal and reverse mark, synchronized ). In receiving point, we make same sequence with the input one and take crosscorrelation function between M-sequence and the received signal. We can see transfer fanctions of plural paths between inputs and a output taps separated from different of delay times on the crosscorrelation function, and from these transfer fanctions, so we compare them when fault occurred with in usual.

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Logic Circuit Fault Models Detectable by Neural Network Diagnosis

  • Tatsumi, Hisayuki;Murai, Yasuyuki;Tsuji, Hiroyuki;Tokumasu, Shinji;Miyakawa, Masahiro
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.154-157
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    • 2003
  • In order for testing faults of combinatorial logic circuit, the authors have developed a new diagnosis method: "Neural Network (NN) fault diagnosis", based on fm error back propagation functions. This method has proved the capability to test gate faults of wider range including so called SSA (single stuck-at) faults, without assuming neither any set of test data nor diagnosis dictionaries. In this paper, it is further shown that what kind of fault models can be detected in the NN fault diagnosis, and the simply modified one can extend to test delay faults, e.g. logic hazard as long as the delays are confined to those due to gates, not to signal lines.

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The plan for fault coordination improvement of underground distribution line (지중 배전선로의 보호협조 개선방안)

  • Ha, Bok-Mam;Yoon, Tae-Sang;Ilm, Seong-Il;Kang, Mun-Ho;Jeong, Chang-Soo;Lee, Heung-Ho
    • Proceedings of the KIEE Conference
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    • 2001.05a
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    • pp.132-135
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    • 2001
  • To improve the fault coordination of underground distribution line we study the several contents such as the magnitude of fault current in distribution line tripping time of CB by acting of over current relay with instantaneous trip and time delay trip. We also examine the melting time of current limiting fuse inside power fuse Through the research as above. we suggest the modification scheme of fault coordination to reduce the interruption times of power failure.

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The Self-Fault Restoration Methodology based on the Recloser in the Distribution Systems (배전계통 리클로우저 기반의 자율적 고장복구 방법론)

  • Ko, Yun-Seok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.9
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    • pp.1681-1688
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    • 2009
  • This paper proposes a new fault restoration method which adopts the recloser as top agent to release the problems of the data concentration and fault processing delay of the existing DAS(distribution Automation System) under the ubiquitous distribution system. In proposed method, top agent collects the data based on the multi-casting communication with the tie switches of the interconnection point, and then selects a closed switch(tie switch) to transfer the sound outage load to other feeders based on the heuristic search strategy step by step until the load transfer work is finished. Here, a new heuristic rule is developed which can guarantee the relational load balancing and line loss from the collected voltage data. Finally, the several faults are simulated for typical multi-section and multi-interconnection distribution system to prove the effectiveness of the proposed strategy, in particular, for each simulation cases, the load balancing index and line loss index of the obtained solution from the proposed method is compared with those of all of feasible solutions.

Interconnect Delay Fault Test in Boards and SoCs with Multiple System Clocks (다중 시스템 클럭으로 동작하는 보드 및 SoC의 연결선 지연 고장 테스트)

  • Lee Hyunbean;Kim Younghun;Park Sungju;Park Changwon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.37-44
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    • 2006
  • This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

Analysis of Transmission Delay and Fault Recovery Performance with EtherCAT for In-Vehicle Network (차량내 통신을 위한 EtherCAT 네트워크의 전송지연 및 고장복구 특성 분석)

  • Kim, Dong-Gil;Jo, Youngyun;Lee, Dongik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37C no.11
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    • pp.1036-1044
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    • 2012
  • Thanks to progressive development of IT technology, the number of intelligent devices communicating each other through an In-Vehicle Network(IVN) has been steadily increasing. It is expected that the required network bandwidth and network nodes for vehicle control in 2015 will be increased by two times and one and half times as compared to in 2010, respectively. As a result, many researchers in automotive industry has showed a significant interest on industrial Ethernets, such as EtherCAT and TTEthernet. This paper addresses an analysis on transmission delay and fault recovery performance with an EtherCAT network which is being considered as an IVN. A mathematical model based on the analysis is verified through a set of experiments using an experimental network setup.

Tele-test Systems for ASIC Design (ASIC 설계를 위한 원격 테스트 시스템)

  • 윤도현;강성호
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.939-942
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    • 1999
  • In this paper, Tele-Test System for ASIC Design is constructed. It consists of the server, and the clients. The server and clients are implemented by Java. Using Java RMI system, the remote access via information network is implemented. In this Tele-test system, fault simulation, test pattern compaction, test pattern generation, and path-delay fault test generation services are implemented. All service can be peformed parallel by network access.

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