• 제어로봇시스템학회:학술대회논문집
• /
• 1994.10a
• /
• pp.7-12
• /
• 1994

This paper describes an outline of pseudorandom M-sequence and its applications to measurement and control engineering. At first, generation and properties of M-sequence is briefly described and then its applications to delay time measurement, information transmission by use of M-array, two dimensional positioning, fault detection of logical circuit, fault detection of RAM, linear and nonlinear system identification.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.9
• /
• pp.1802-1808
• /
• 2009

A fault detection observer with finite time convergence characteristics(FT_FDO) is proposed and applied to a fault detection isolation system for a dynamic control system. The FT_FDO is a kind of dual state-observer scheme that provides with the state estimates insensitive to a specified fault and the corresponding fault estimate. The state estimates are processed to get the residual that will be logically compared with other residuals to detect and isolate the fault of interest, and the fault estimate may be used for fault compensation. The FDIS employing the FT_FDOs can be considered to be a multiple observer schemes(MOS) in which FT_FDOs are parallelly driven to generate a set of residuals to be compared each other. Due to the finite time convergence characteristics of the FT_FDO, the predetermined detection delay can be considered in the design stage of FDIS so that any fault of interest can be detected and identified in that time. It evidently resolves a well known difficulty of threshold selection owing to the transient responses of the fault detection observers(FDO) employed in FDIS. An FDIS is constructed for instruments(2-sensor, 1-actuator) in an inverted pendulum control system, and simulations are performed to show the performance of the FDIS and fault tolerant control system.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.62 no.1
• /
• pp.12-17
• /
• 2013

Fault currents are expressed as a combination of harmonic components and exponentially decaying DC offset components, during the occurrence of fault in power system. The DC offset components are included, when the voltage phase angle of fault inception is closer to $0^{\circ}$ or $180^{\circ}$. The digital protection relay should be detected quickly and accurately during the faults, despite of the distortions of relaying signal by these components. It is very important to implement the robust protection algorithm, that is not affected by DC offset and harmonic components, because most relaying algorithms extract the fundamental frequency component from distorted relaying signal. So, In order to high performance in relaying, advanced DC offset removal filter is required. In this paper, a new DC offset removal filter, which is no need to preset a time constant of power system and accurately estimate the DC offset components with one cycle of data, is proposed, and compared with the other filter. In order to verify performance of the filter, we used collecting the current signals after synchronous machine modeling by ATPDraw5.7p4 software. The results of simulation, the proposed DC offset removal filter do not need any prior information, the phase delay and gain error were not occurred.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.5_6
• /
• pp.265-272
• /
• 2003

As VLSI systems become integrated at large-scale, logic fault or delay fault may result from crosstalk noise originated from cross coupling capacitance which exists between two adjacent wires. Because designers in industry do not have means to prevent crosstalk problems, they should check and adjust unsatisfactory designs after all designs are completed, if necessary. In this paper, we analyze how spacing, slew rate, line width, and line length influence the crosstalk, and suggest some solutions for the various factors that nay cause crosstalk problems. we also propose how to optimize the designs by using standardization of noise tables.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.6
• /
• pp.72-84
• /
• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.11
• /
• pp.1873-1878
• /
• 2007

Current differential relays may maloperate during magnetic inrush and over-excitation because a significant differential current is produced. To prevent maloperation, the relays adopt some harmonic components included in the differential current. The harmonic restraints may increase the security of a relay but cause the operating time delay of a relay when an internal fault occurs. Moreover, the operating time delay is more increased if a current transformer (CT) is saturated. This paper describes a current differential relaying algorithm for power transformer protection with a compensating algorithm for the secondary current of a CT. The comparative study was conducted with and without the compensating algorithm. The performance of the proposed algorithm was investigated when the measurement CT (C400) and the protection CT (C400) are used. The proposed algorithm can compensate the distorted current of a CT and thus reduce the operating time delay of the relay significantly for an internal fault with CT saturation.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.10
• /
• pp.3226-3235
• /
• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.65 no.6
• /
• pp.955-961
• /
• 2016

Fault location estimation is an important element for rapid recovery of power system when fault occur in transmission line. In order to calculate line impedance, most of fault location algorithm uses by measuring relaying waveform using DFT. So if there is a calculation error due to the influence of phasor by DC offset component, due to large vibration by line impedance computation, abnormal and non-operation of fault locator can be issue. It is very important to implement the robust fault location algorithm that is not affected by DC offset component. This paper describes an enhanced fault location algorithm based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any erstwhile information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced fault location algorithm uses DFT filter as well as the proposed DC offset filter. The behavior of the proposed fault location algorithm using off-line simulation has been verified by data about several fault conditions generated by the ATP simulation program.

• Proceedings of the KIEE Conference
• /
• 2001.05a
• /
• pp.226-229
• /
• 2001

The combined transmission lines with the underground power cables are continuously expanded in power systems. So the fault of combined transmission line is increased every year as the complication of underground transmission line. In this paper. traveling wave theory and DWT wavelet transform are used for fast and accurate detection of fault location at the combined transmission line. Traveling wave travels to each bus like surge and repeats reflection and transmission till transient signal is completely disappeared. When fault is occurred on overhead and underground tine, the fault location detecting algorithm was performed with using continuous peak value time-delay of traveling wave reflected from A bus.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.6
• /
• pp.859-868
• /
• 2012

A new fault location algorithm based on stationary wavelet transform and its verification experiment results are described for HVDC submarine cables in this paper. For wavelet based fault location algorithm, firstly, 4th level approximation coefficients decomposed by wavelet transform function are superimposed by correlation, then the distance to the fault point is calculated by time delay between the first incident signal and the second reflected signal. For the verification of this algorithm, the real experiments based on various fault conditions and return types of fault current are performed at HVDC submarine cable test yard located in KEPCO(Korea Electric Power Corporation) Power Testing Center of South Korea. It proves that the fault location method proposed in this paper is very simple but very quick and accurate for HVDC submarine cable fault location.