• International Journal of Control, Automation, and Systems
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• v.6 no.2
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• pp.149-159
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• 2008

This paper considers the problem of adaptive fault-tolerant guaranteed cost controller design via dynamic output feedback for a class of linear time-delay systems against actuator faults. A new variable gain controller is established, whose gains are tuned by the designed adaptive laws. More relaxed sufficient conditions are derived in terms of linear matrix inequalities (LMIs), compared with the corresponding fault-tolerant controller with fixed gains. A real application example about river pollution process is presented to show the effectiveness of the proposed method.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.19-21
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• 2009

The reflectometry for locating the fault at a cable is the same as a problem estimating the time delay between the incident and the reflected signals. In this paper, we propose a method for estimating the time delay between the two signals. The proposed method is based on the modeling of the Gaussian enveloped linear chirp signal in the Gaussian noise environment. The phase and the instantaneous frequency of the received signal are estimated by linear Kalman filtering. From the estimated instantaneous frequency, we can measure the time interval between the center frequencies of the incident and the reflected signals. The time interval is the same as the time delay between the incident and the reflected signals. In a simulation assuming that the cable has open fault at the end of the cable, the proposed method showed a good result in estimating the time delay.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.12
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• pp.54-60
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• 2005

In this paper, fault tolerant control for aircraft is being discussed. The authors propose a fault tolerant control algorithm based on time delay control. Time delay control is an effective method to deal with unknown dynamics. The proposed algorithm has no parameter to be updated and needs no prior information of faults. These are the primary advantages of the proposed method. The algorithm uses output feedback. The design and the stability condition are presented by following the existing proof. The proposed algorithms are verified by simulation examples.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• International Journal of Control, Automation, and Systems
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• v.1 no.3
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• pp.308-314
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• 2003

This paper presents a serial communication based fault diagnosis scheme for a brushless DC (BLDC) motor using parameter estimation and Bayes classifier. The presented scheme consists of a smart network board, and a fault detection and isolation (FDI) master. The smart network board is installed near the BLDC motor drive system to acquire motor data and transmit motor data to the FDI-master via serial communication channel. The FDI-master estimates BLDC motor resistance to detect symptom of faults, and assign symptom to fault type using Bayes classifier. In this scheme, since communication time delay has a serious effect on performance, periodic and fixed communication protocol is designed. Hence, the delay time is priory known. By experiment result, presented scheme was verified.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.279-286
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• 2006

A method for estimating the instantaneous phasor of a fault current signal is proposed for high-speed distance protection that is immune to a DC-offset. The method uses a modified notch filter in order to eliminate the power frequency component from the fault current signal. Since the output of the modified notch filter is the delayed DC-offset, delay compensation results in the same waveform as the original DC-offset. Subtracting the obtained DC-offset from the fault current signal yields a sinusoidal waveform, which becomes the real part of the instantaneous phasor. The imaginary part of the instantaneous phasor is based on the first difference of the fault current signal. Since a DC-offset also appears in the first difference, the DC-offset is removed trom the first difference using the results of the delay compensation. The performance of the proposed method was evaluated for a-phase to ground faults on a 345kV 100km overhead transmission line. The Electromagnetic Transient Program was utilized to generate fault current signals for different fault locations and fault inception angles. The performance evaluation showed that the proposed method can estimate the instantaneous phasor of a fault current signal with high speed and high accuracy.

• International Journal of Aeronautical and Space Sciences
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• v.17 no.1
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• pp.54-63
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• 2016

A novel attitude tacking control method using Time Delay Control (TDC) scheme is developed to provide robust controllability of a rigid hexacopter in case of single or multiple rotor faults. When the TDC scheme is developed, the rotor faults such as the abrupt and/or incipient rotor faults are considered as model uncertainties. The kinematics, modeling of rigid dynamics of hexacopter, and design of stability and controllability augmentation system (SCAS) are addressed rigorously in this paper. In order to compare the developed control scheme to a conventional control method, a nonlinear numerical simulation has been performed and the attitude tracking performance has been compared between the two methods considering the single and multiple rotor faults cases. The developed control scheme shows superior stability and robust controllability of a hexacopter that is subjected to one or multiple rotor faults and external disturbance, i.e., wind shear, gust, and turbulence.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.89-98
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• 1994

In this paper, a criteria for selecting an appropriate load redistribution algorithm is devised so that a fault-tolerance distributed system can operte at its optimal efficience. To present the guideline for selecting redistributing algorithms, simulation models of fault-tolerant system including redistribution algorithms are developed using SLAM II. The job arrival rate, service rate, failure and repair rate of nodes, and communication delay time due to load migration are used as parameters of simulation. The result of simulation shows that the job arrival rate and the failure rate of nodes are not deciding factors in affecting the relative efficiency of algorithms. Algorithm B shows relatively a consistent performance under various environments, although its performance is between those of other algorithms. If the communication delay time is longer than average job processing time, the performance of algorithm B is better than others. If the repair rate is relatively small or communication delay time is longer than service time, algorithm A leads to good performance. But in opposite environments, algorithm C is superior to other algorithms.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.