• Journal of Advanced Navigation Technology
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• v.6 no.2
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• pp.130-137
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• 2002

We present Space-Time Trellis Coded Code Division Multiple Access systems, which maintain the full diversity and coding gain of Space-Time Trellis Codes(STTC) and have the immunity to performance degradation caused by multipath fading. These STTC CDMA systems are constructed by adding the spreading and despreading processes of PN codes to STTC systems. In multipath fading channels, delay spreaded signals are detected and combined, then decoded. According to the combining and decoding methods, there are four decoding methods. There are optimum ML decoding without combining, adding multipath signals in each receive antenna before decoding, combining multi path signals in each antenna before decoding, and combining all received signals before decoding. Performance of these methods is proportional to complexity. Besides, all methods are shown to compensate the irreducible error rate which appears in multipath fading channels.

• The KIPS Transactions:PartC
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• v.11C no.3
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• pp.353-360
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• 2004

In this Paper, We propose an efficient iteration decoding control method with variable iteration decoding of iteration codes decoding using Cyclic Redundancy Check. As the number of iterations increases, the bit error rate and frame error rate of the decoder decrease and the incremental improvement gradually diminishes. However, when the iteration decoding number is increased, it require much delay and amount of processing time for decoding. Also, It can be observed the error nor that the performance cannot be improved even though increasing of the number of iterations and SNR. So, Suitable number of iterations for stopping criterion is required. we propose variable iteration control method to adapt variation of channel using Frame Error-Check indicator. Therefore, the amount of computation and the number of iterations required for iteration decoding with CRC method can be reduced without sacrificing performance.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2465-2473
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• 2012

Recently, as one of low complexity video encoding methods, DVC (Distributed Video Coding) scheme has been actively studied. Most of DVC schemes exploit feedback channel to achieve better coding performances, however, this causes these schemes to have high decoding delay. In order to overcome these, this paper proposes a new fast DVC decoding method using parity-bit request model, which can be obtained by using bit-error rate, sent by encoder with motion vector, which is transmitted through feedback channel by decoder after generating side information. Through several simulations, it is shown that the proposed method improves greatly the decoding speed, compared to the conventional schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.39-48
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• 2004

Turbo codes, whose performance in bit error rate is close to the Shannon limit, have been adopted as a part of standard for the third-generation high-speed wireless data services. Iterative Turbo decoding results in decoding delay and high power consumption. As wireless communication systems can only use limited power supply, low power design techniques are essential for mobile device implementation. This paper proposes new effective criteria for stopping the iteration process in turbo decoding to reduce power consumption. By setting two stopping criteria, decodable threshold and undecodable threshold, we can effectively reduce the number of decoding iterations with only negligible error-correcting performance degradation. Simulation results show that the number of unsuccessful error-correction can be reduced by 89% and the number of decoding iterations can be reduced by 29% on the average among 12500 simulations when compared with those of an existing typical method.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.4
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• pp.430-435
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• 2018

In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1387-1394
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• 2004

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication systems. And it is well known about the fact that turbo code has better the BER performance as the number of decoding iterations increases in the AWGN channel environment. However, as the number of decoding iterations is increased under the several channel environments, any further iteration results in very little improvement, and it requires much delay, computation and power consumption in proportion to the number of decoding iterations. In this paper, it proposes the efficient iterative decoding stop criterion algorithm which can largely reduce the average number of decoding iterations of turbo code. Through simulations, it is verifying that the proposed algorithm can efficiently stop the iterative decoding by using the variance value of error probability for the soft output value, and can largely reduce the average number of decoding iterations without BER performance degradation. As a result of simulation, the average number of decoding iterations for the proposed algorithm is reduced by about 2.25% ~14.31％ and 3.79％ ~14.38% respectively compared to conventional schemes, and power consumption is saved in proportion to the number of decoding iterations.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.314-319
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• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (COMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) is considered In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical COMA network can be substantially improved by increasing the interleaver length and the number of iterations in the decoding process. The results of this paper can be applied to implement the indoor optical wireless LANs.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.9-16
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• 2004

This paper proposes a performance analysis model of security servers comprising IPSec accelerators. The proposed model is based on a M/M1 queueing system with traffic load of Poisson distribution. The decoding delay has been defined to cover parameters characterizing hardware of security sorrels. Decoding delay values of a commercial IPSec accelerator are extracted yielding less than 15% differences from measured data. The extracted data are used to simulate the server system with the proposed model. The simulated performance of the cryptographic processor BCM5820 is around 75% of the published claimed level. The performance degradation of 3.125% and 14.28% are observed for 64byte packets and 1024byte packets, respectively.

• The KIPS Transactions:PartC
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• v.19C no.4
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• pp.247-252
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• 2012

Network coding has been shown to improve various performance metrics in network systems. However, if network coding is implemented as software a huge time delay may be incurred at encoding/decoding stage so it is imperative for network coding to be parallelized to reduce time delay when encoding/decoding. In this paper, we compare the performance of parallelized decoders for random linear network coding (RLC) and pipeline network coding (PNC), a recent development in order to alleviate problems of RLC. We also compare multi-threaded algorithms on multi-core CPUs and massively parallelized algorithms on GPGPU for PNC/RLC.