• 제목/요약/키워드: current amplifier

검색결과 611건 처리시간 0.026초

Design of Voltage Controlled Oscillator using Miller Effect

  • Choi Moon-Ho;Kim Yeong-Seuk
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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    • pp.218-220
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    • 2004
  • A new wide-band VCO topology using Miller capacitance is proposed. Contrary to conventional VCO using the Miller capacitance where the variable amplifier gain is negative, the proposed VCO uses both the negative and positive variable amplifier gain to enhance the frequency tuning range significantly. The proposed VCO is simulated using HSPICE. The simulations show that 410MHz and 220MHz frequency tuning range are obtained using the negative .and positive variable amplifier gain, respectively. The tuning range of the proposed VCO is $23\%$ of the center frequency(2.8GHz). The phase noise is -104dBc/Hz at 1MHz offset by simple model. The operating current is only 3.84mA at 2.5V power supply.

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저전압용 CMOS 연산 증폭기를 위한 전력 최소화 기법 및 그 응용 (A power-reduction technique and its application for a low-voltage CMOS operational amplifier)

  • 장동영;이용미;이승훈
    • 전자공학회논문지C
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    • 제34C권6호
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    • pp.37-43
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    • 1997
  • In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

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Fabry-Perot 공진기형 AlGaAs 반도체 레이저 증폭기의 이득특성 (Gain Characteristics of Fabry-Perot Type AlGaAs Semiconductor Laser Amplifier)

  • 김도훈;권진혁
    • 한국광학회지
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    • 제2권2호
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    • pp.67-73
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    • 1991
  • 단일 종모드로 동작하며, 10mW의 출력을 가지는 AlGaAs 반도체 레이저를 이용하여 Fabry-Perot 공진기형 레이저 증폭기 시스템을 구성하고 비포화 신호이득(unsaturated signal gain), 신호이득 대역폭(signal gain bandwidth), 포화출력(saturation power)을 측정하였다. 증폭기 레이저의 펌핑전류에 따른 비포화 신호 이득은 발진 문턱 전류 근처에서 $0.7\mu\textrmW$의 레이저 출력을 증폭기 레이저에 입사시켰을 때 최대 25dB을 얻었으며 이때 신호이득의 대역폭이 3 GHz 정도임을 확인하였다. 또한 입력 세기(input power)에 따른 비포화 신호이득의 변화를 측정하고 이때의 포화출력을 측정하였다.

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이중 부궤환에 의한 고효율 광대역 D급 오디오 증폭기 (Class D Audio Power Amplifier with High Efficiency and Wide Bandwidth by Dual Negative Feedback)

  • 정재훈;성환호;이정한;조규형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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    • pp.141-143
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    • 1994
  • The pulse width modulated class D power amplifier has the highest efficiency among various class amplifiers but the performances, such as bandwidth, distortion and stability are inferior to the conventional ones. In this paper, a new class D amplifier design is Presented employing dual feedback loops namely current and voltage feedback. The new design provides wide full-power bandwidth and stability at any load with high efficiency.

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Design of an Nd:YAG Slab Structure for a High-power Zigzag Slab Laser Amplifier Based on a Wavefront Simulation

  • Shin, Jae Sung;Cha, Yong-Ho;Cha, Byung Heon
    • Current Optics and Photonics
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    • 제3권3호
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    • pp.236-242
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    • 2019
  • An Nd:YAG slab structure was designed for a high-power zigzag slab laser amplifier based on computational simulation of the wavefront distortion. For the simulation, the temperature distribution in the slab was calculated at first by thermal analysis. Then, the optical path length (OPL) was obtained by a ray tracing method for the corresponding refractive index variation inside the slab. After that, the OPL distribution of the double-pass amplified beam was calculated by summing the results obtained for the first and second passes. The amount of wavefront distortion was finally obtained as the peak-to-valley value of the OPL distribution. As a result of this study, the length and position of the gain medium were optimized by minimizing the transverse wavefront distortion. Under the optimized conditions, the transverse wavefront distortion of the double-pass amplified beam was less than $0.2{\mu}m$ for pump power of 14 kW.

Metamorphic HEMT를 이용한 100GHz MIMIC 증폭기의 설계 및 제작 (Design and Fabrication of 100 GHz MIMIC Amplifier Using Metamorphic HEMT)

  • 안단;이복형;임병옥;이문교;백용현;채연식;박형무;이진구
    • 대한전자공학회논문지SD
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    • 제41권9호
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    • pp.25-30
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    • 2004
  • 본 논문에서는 0.1㎛ InGaAs/InAlAs/GaAs Metamorphic HEMT (High Electron Mobility Transistor)를 이용하여 100 GHz 대역의 MIMIC(Millimeter-wave Monolithic Integrated Circuit) 증폭기를 설계 및 제작하였다. MIMIC 증폭기의 제작을 위해 Metamorphic HEMT(MHEMT)를 설계 및 제작하였으며, 제작된 MHEMT의 드레인 전류 밀도는 640 mA/mm 최대 전달컨덕턴스(Gm)는 653 mS/mm를 얻었으며, RF 특성으로 fT는 173 GHz, fmax는 271 GHz의 양호한 성능을 나타내었다. 100 GHz MIMIC 증폭기의 개발을 위해 MHEMT의 소신호 모델과 CPW 라이브러리를 구축하였으며, 이를 이용하여 MIMIC 증폭기를 설계하였다. 설계된 증폭기는 본 연구에서 개발된 MHEMT MIMIC 공정을 이용해 제작되었으며, 100 GHz MIMIC 증폭기의 측정결과, 100 GHz에서 10.1 dB 및 97.8 Gllz에서 12.74 dB의 양호한 S21 이득 특성을 나타내었다.

의료기기용 MedRadio 대역 저전력 저잡음 증폭기 (A MedRadio-Band Low Power Low Noise Amplifier for Medical Devices)

  • 김태종;권구덕
    • 전자공학회논문지
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    • 제53권9호
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    • pp.62-66
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    • 2016
  • 본 논문에서는 의료기기용 MedRadio 대역의 저전력 저잡음 증폭기를 제안한다. 제안한 저잡음 증폭기는 전류 재사용 저항 피드백 증폭기 구조를 채택하여 $g_m$을 증폭시키고 소스 인덕터 없이 입력 매칭을 가능하도록 하였다. 추가적으로 제안한 직렬 저항, 인덕터, 커패시터 입력 매칭 네트워크의 Q-factor를 통해 저잡음 증폭기의 전압 이득을 증가시켜 잡음 지수를 최소화 했다. 로드저항이 없는 구조를 채택하여 낮은 전원 전압으로 전력 소모를 줄였다. 제안한 MedRadio 대역 저전력 저잡음 증폭기는 $0.13{\mu}m$ CMOS 공정을 사용하여 설계하였고, 전원 전압 1 V에서 0.18 mA의 전류를 소모하면서 0.85 dB의 잡음 지수, 30 dB의 전압 이득, -7.9 dBm의 IIP3의 성능을 보인다.

A Highly Efficient Dual-Mode 3G/4G Linear CMOS Stacked-FET Power Amplifier Using Active-Bypass

  • Kim, Unha;Kim, Yong-Gwan;Woo, Jung-Lin;Park, Sunghwan;Kwon, Youngwoo
    • Journal of electromagnetic engineering and science
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    • 제14권4호
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    • pp.393-398
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    • 2014
  • A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

Evaluation of GaN Transistors Having Two Different Gate-Lengths for Class-S PA Design

  • Park, Jun-Chul;Yoo, Chan-Sei;Kim, Dongsu;Lee, Woo-Sung;Yook, Jong-Gwan
    • Journal of electromagnetic engineering and science
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    • 제14권3호
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    • pp.284-292
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    • 2014
  • This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계 (Design of UWB CMOS Low Noise Amplifier Using Inductor Peaking Technique)

  • 성영규;윤경식
    • 한국정보통신학회논문지
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    • 제17권1호
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    • pp.158-165
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    • 2013
  • 본 논문에서는 3.1-10.6GHz 초광대역 CMOS 저잡음 증폭기의 새로운 구조를 소개하였다. 제안된 초광대역 저잡음 증폭기는 입력 임피던스 정합에 RC 피드백과LC 필터회로를 사용하여 설계되었다. 이 설계에 전류 재사용 구조는 전력소비를 줄이기 위해 채택되었으며, 인덕터 피킹 기법은 대역폭을 확장하기 위하여 적용되었다. 이 초광대역 저잡음 증폭기의 특성을 $0.18-{\mu}m$ CMOS 공정기술로 시뮬레이션을 수행한 결과는 3.1-10.6GHz 대역 내에서 전력이득은 14-14.9dB, 입력정합은 -10.8dB이하, 평탄도는 0.9dB, 잡음지수는 2.7-3.3dB인 것을 보여준다. 또한, 입력 IP3는 -5dBm이고, 소비전력은 12.5mW이다.