• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.948-950
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• 2002

IPSec authentication provides support for data integrity and authentication of IP packets. Authentication is based on the use of a message authentication code(MAC). Hash function algorithm is used to produce MAC , which is referred to HMAC. In this paper, we propose a cryptographic accelerator using FPGA implementations. The accelator consists of a hash function mechanism based on MD5 algorithm, and a public-key generator based on a Elliptiv Curve algorithm with small scale of circuits. The accelator provides a messsage authentification as well as a digital signature. Implementation results show the proposed cryptographic accelerator can be applied to IPSec authentications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.852-855
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• 2005

This paper introduces a case study of designing a cryptographic processor dedicated to VPN/SSL system. The designed processor supports not only block cipher algorithm, including 3DES, AES, and SEED, but also 163 bit ECC public key crypto algorithm. Moreover, we adopted PCI Master interface in the design, which guarantees fast computation of cryptographic algorithm prevalent in general information security systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2713-2717
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• 2011

To transmit data from straggling sensors in water-processing basic industries etc., used Binary-CDMA system has safety voluntarily. But Binary-CDMA is necessity that react very sensitively in environment change as defense about hacking and cracking of various way that change suddenly. Therefore, this paper is that see added cryptographic algorithm for safety and easy update on correlator that a bottle-neck phenomenon is happened in Binary-CDMA to solve problem that is such. Added cryptographic algorithm does to communicate safe information in channel that is not safe as that achieve 1:1 confrontation for sensors by symmetric cryptographic algorithm.

• International Journal of Computer Science & Network Security
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• v.23 no.7
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• pp.49-60
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• 2023

The amount of data generated by electronic systems through e-commerce, social networks, and data computation has risen. However, the security of data has always been a challenge. The problem is not with the quantity of data but how to secure the data by ensuring its confidentiality and privacy. Though there are several research on cloud data security, this study proposes a security scheme with the lowest execution time. The approach employs a non-linear time complexity to achieve data confidentiality and privacy. A symmetric algorithm dubbed the Non-Deterministic Cryptographic Scheme (NCS) is proposed to address the increased execution time of existing cryptographic schemes. NCS has linear time complexity with a low and unpredicted trend of execution times. It achieves confidentiality and privacy of data on the cloud by converting the plaintext into Ciphertext with a small number of iterations thereby decreasing the execution time but with high security. The algorithm is based on Good Prime Numbers, Linear Congruential Generator (LGC), Sliding Window Algorithm (SWA), and XOR gate. For the implementation in C, thirty different execution times were performed and their average was taken. A comparative analysis of the NCS was performed against AES, DES, and RSA algorithms based on key sizes of 128kb, 256kb, and 512kb using the dataset from Kaggle. The results showed the proposed NCS execution times were lower in comparison to AES, which had better execution time than DES with RSA having the longest. Contrary, to existing knowledge that execution time is relative to data size, the results obtained from the experiment indicated otherwise for the proposed NCS algorithm. With data sizes of 128kb, 256kb, and 512kb, the execution times in milliseconds were 38, 711, and 378 respectively. This validates the NCS as a Non-Deterministic Cryptographic Algorithm. The study findings hence are in support of the argument that data size does not determine the execution.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.3
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• pp.65-78
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• 1997

Due to the cryptographic functional structure including the S-box, DES is not robust against differential cryptoanalysis (DC). Therefore, to increase the security against DC, we have to redesign the S-box or modify DES algorithm to decrease the probability for the N-1 round characteristics. However, it has been shown that a new design for the S-box is not secure enough. Rather, if will be more reliable to devise a modified cryptographic algorithm. In this paper, we propose a modified DES algorithm to decrease the probability of N-1 round characteristics to be robust against DC. According to our comparative study, the proposed algorithm is shown to be more robust against the DC than DES.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.285-288
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• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.805-810
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• 2012

Recently, applications range of NFC is widening by popularization of smartphone. Expansion of NFC means generalization of electronic payments systems. So security of NFC is very important. AES-128 is safe cryptographic technique for NFC now in use. But, the more range of applications increases, the more safe cryptographic techniques are necessary. In this paper, we propose the safe method is unaffected by the development of NFC. Proposed A-NFC scheme, adding the authentication of asymmetric cryptographic, is easy to apply for NFC and NFC-USIM chipsets, and it can adapt to the general NFC environment.

• The KIPS Transactions:PartC
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• v.12C no.4 s.100
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• pp.495-502
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• 2005

Cryptographic algorithm testing is performed to ensure that a specific algorithm implementation is implemented correctly and functions correctly. CMVP(Cryptographic Module Validation Program) of NIST in US is the well-known testing system that validates cryptographic modules to Federal Information Processing Standards (FIPS). There is no FIPS-approved stream cipher, and CMVP doesn't involve its validation testing procedure. In this paper we provide validation systems for three currently used light-weight stream ciphers: Bluetooth encryption algorithm E0, 3GPP encryption algorithm A5/3, and RC4 used for WEP and SSL/TLS Protocols. Moreover we describe our validation tools implemented by JAVA programing.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.