• Tribology and Lubricants
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• v.21 no.6
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• pp.256-262
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• 2005

The calculation of bump foil deflection is very important to predict the performance of foil bearings more accurately, because the foil bearings consist of top foil and its elastic foundation usually called bump foil. For the purpose of this, a finite element model considering 3-dimensional structure of the bump foil is developed to calculate the deflection of inter-connected bump. The results obtained from the suggested model are compared and analyzed with those from the previous proposed deflection models. In addition, load capacity of the foil bearings is analyzed by using this model.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.10a
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• pp.91-96
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• 2001

When it is considered that many vehicle rides on the road and ride quality is an important method to evaluate vehicle performance with handling, running-over-bump manoeuvre may be suitable for testing ride quality. In this paper, a computed model has roughly steering system and lumped mass, connected by joint each rigid body, and suspension that has beam elements and has shock absorber as force element to represent nonlinear characteristics. A computer simulations for passing over a bump were made with two velocities. One side of vehicle passed over bump in due consideration of driver's habit that driver is subject to avoid a bad ride quality. On simulation, vertical acceleration, pitch angle and roll angle were measured at the mass center of chassis each case.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.9
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• pp.1-5
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• 1999

In this paper, we proposed a novel branch-line coupler using filp-chip technology. The proposed coupler consists of CPW and inverted microstrip. The CPW is on the GaAs flip-chip substrate, and the inverted microstrip is on the alumina main substrate. The ground plane of the CPW is used as a ground plane of the inverted microstrip. And both the transmission lines are connected by solder bump with each other. The characteristics of thisstructure was calculated by FDTD method. The S21, S31 are -3dB and the phase difference is $90^{\circ}$. The calculated characteristics are the same as those of the regular branch-line coupler. This structure can be applied for various kinds of devices using flipchip technology.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.275-281
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• 2003

A new neural oscillator has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed neural oscillator consists of a nonlinear variable resistor with negative resistance as well as simple transconductors and capacitors. The variable negative resistor which is used as a input stage of the oscillator consists of a positive feedback transconductors and a bump circuit with Gaussian-like I-V curve. The proposed neural oscillator has designed in integrated circuit with SPICE simulations. Simulations of a network of 4 oscillators which are connected with excitatory and inhibitory synapses demonstrate cooperative computation. Measurements of the fabricated oscillator chip with a $\pm$ 2.5 V power supply is shown and compared with the simulated results.

• Tribology and Lubricants
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• v.39 no.2
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• pp.76-80
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• 2023

This paper describes an experimental investigation of the effect of cooling flow rate on gas foil thrust bearing (GFTB) performance. In a newly developed GFTB test rig, a non-contact type pneumatic cylinder provides static loads to the test GFTB and a high-speed motor rotates a thrust runner up to the maximum speed of 80 krpm. Force sensor, torque arm connected to another force sensor, and thermocouples measures the applied static load, drag torque, and bearing temperature, respectively, for cooling flow rates of 0, 25, and 50 LPM at static loads of 50, 100, and 150 N. The test GFTB with the outer radius of 31.5 mm has six top foils supported on bump foil structures. During the series of tests, the transient responses of the bearing drag torque and bearing temperature are recorded until the bearing temperature converges with time for each cooling flow rate and static load. The test data show that the converged temperature decreases with increasing cooling flow rate and increases with increasing static load. The drag torque and friction coefficient decrease with increasing cooling flow rate, which may be attributed to the decrease in viscosity and lubricant (air) temperature. These test results suggest that an increase in cooling flow rate improves GFTB performance.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.