• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.56-65
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• 2009

As increasing the number of IPs integrated in a single chip and requiring high communication bandwidth on a chip, the trend of SoC communication architecture is changed from bus- or crossbar-based architecture to packet switched network architecture, NoC. However, highly complex control logics in routers require multiple cycles to switch packet. In this paper, we design low complex router to improve the communication latency. Our NoC design is verified by simulation platform modeled by ESL tool, SoC Designer. We also evaluate our NoC design comparing to the previous NoC architecture based on VC router. Our results show that our NoC architecture has less communication latency, even small throughput degradation (about 1-2%).

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.921-924
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• 1993

For the purpose of applying to a high-speed control system, such as engine control for automobile application, we propose an architecture of a fuzzy inference processor, which can realize high-speed inference, high-resolution, and can be implemented with small chip area. We have designed a single chip based on the architecture, and confirmed the performance, such as 140 kFLIPS with 8-bit resolution.

• Journal of the Korean Institute of Landscape Architecture
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• v.22 no.2
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• pp.158-179
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• 1994

• The Transactions of the Korea Information Processing Society
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• v.5 no.10
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• pp.2686-2703
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• 1998

The widening pClformnnce gap between processor and memory causes an emergence of the promising architecture, processor-memory (PM) integration In this paper, various design issues for P-M integration are studied, First, an analytical model of the DRAM access time is constructed considering both the bank conflict ratio and the DRAM page hit ratio. Then the points of both the performance improvement and the perfonnance bottle neck are found by the proposed model as designing on-chip DRAM architectures. This paper proposes the new architecture, called the delayed precharge bank architecture, to improve the perfonnance of memory system as increasing the DRAM page hit ratio. This paper also adapts an efficient bank interleaving mechanism to the proposed architecture. This architecture is verified !II he better than the hierarchical multi-bank architecture as well as the conventional bank architecture by executiun driven simulation. Eight SPEC95 benchmarks are used for simulation as changing parameters for the cache architecture, the number of DRAM banks, and the delayed time quantum.

• Journal of The Korean Digital Architecture Interior Association
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• v.1 no.1
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• pp.16-23
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• 2001

This study is aimed to analyze present states of computer education in interior design dept. and therefore to offer basic data in order to establish middle and long term plan on computer education. According to results of analysis, computer education course accounts for 10.1 percent in total curriculum. But this component ratio has great difference between university and jumopr college. Namely computer education course of college is much more weighter than that of university. It seems to be results from college's characteristic strategies. But this results to unsuitable curriculum allocation. To solve this problem, further examination of linking computer's course with drafting and drawing course should be required. And to heighten more effect of computer education, other circumstance as well as educational facility should be improved and common CAD laboratory should be produced.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.4
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• pp.41-46
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• 2004

This paper presents a new semi- systolic architecture for $AB^2$ operation. First of all the previous architecture proposed by Lee et al. is analysed and then we present a new algorithm and it's architecture for $AB^2$ operation based on AOP (all one polynomial) to solve the shortcomings in the architecture. Proposed architecture has an efficient configuration than other previous architectures. It is useful for implementing the exponentiation architecture, which is the core operation in public-key cryptosystems.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.1
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• pp.33-41
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• 2016

Big data management is becoming an increasingly important issue in both industry and academia of information science community today. One of the important categories of big data generated from software systems is log data. Log data is generally used for better services in various service providers and can also be used to improve system reliability. In this paper, we propose a novel big data management architecture specialized for log data. The proposed architecture provides a scalable log management system that consists of client and server side modules for efficient handling of log data. To support large and simultaneous log data from multiple clients, we adopt the Hadoop infrastructure in the server-side file system for storing and managing log data efficiently. We implement the proposed architecture to support various client environments and validate the efficiency through measurement studies. The results show that the proposed architecture performs better than the existing logging architecture by 42.8% on average. All components of the proposed architecture are implemented based on open source software and the developed prototypes are now publicly available.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.5
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• pp.1421-1444
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• 2012

Mobile devices such as Android devices are emerging as a convenient client computing device with mobility and context-sensing capability. However, the computing power and hardware resource of the devices are limited due to their small form-factor. Consequently, large-scaled applications could not be deployed on these devices. Nonetheless, if the large-scaled applications are deployed and executed on the devices, high performance of the applications cannot be guaranteed. To remedy the limitation in terms of performance, it is inevitable to let some heavy-weight functionality executed on the server side and let a client application invoke the functionality in the server. To realize this kind of mobile applications, we adopt well-defined architecture design principles; being thin-client, being layered with Model-View-Controller (MVC), and being balanced between client side and server side. By adopting the principles, we propose a unique, ideal and practical architecture for mobile applications, called balanced MVC architecture. By considering the principles, key design considerations of realizing balanced MVC architecture lie in functionality partitioning. Hence, we define key criteria of determining the degree of performance. And, we define a method to design a balanced MVC architecture which embodies functionality partitioning for high performance, and a simulation-based evaluation method of balanced MVC architectures.

• International Journal of Computer Science & Network Security
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• v.24 no.7
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• pp.1-10
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• 2024

Software architecture are High-level design decisions shaping a software system's components, structure, and interactions. It can be a blueprint for development, evolution, and ongoing maintenance. This research investigates the communication practices employed by software architects and developers to ensure adherence to the designed software architecture. It explores the factors influencing the selection of follow-up methods and the impact of follow-up frequency on successful implementation. Findings reveal that formalized follow-up procedures are not yet a ubiquitous element within the software development lifecycle. While electronic communication, particularly email, appears to be the preferred method for both architects and developers, physical and online meetings are utilized less frequently. Interestingly, the study suggests a potential confidence gap, with architects expressing concerns about developers' ability to faithfully implement the architecture. This may lead to architects providing additional clarification. Conversely, while most developers reported confidence in their software knowledge, overly detailed architecture documentation may pose challenges, highlighting the need for architects to consider alternative communication strategies. A key limitation of this study is the sample size, restricting the generalizability of the conclusions. However, the research offers valuable preliminary insights into the communication practices employed for architecture implementation, paving the way for further investigation with a larger and more diverse participant pool.