• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.8
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.837-852
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• 2021

Recurrent neural network (RNN) architectures have been used for language modeling (LM) tasks that require learning long-range word or character sequences. However, the RNN architecture is still suffered from unstable gradients on long-range sequences. To address the issue of long-range sequences, an attention mechanism has been used, showing state-of-the-art (SOTA) performance in all LM tasks. A differentiable neural computer (DNC) is a deep learning architecture using an attention mechanism. The DNC architecture is a neural network augmented with a content-addressable external memory. However, in the write operation, some information unrelated to the input word remains in memory. Moreover, DNCs have been found to perform poorly with low numbers of weight parameters. Therefore, we propose a robust memory deallocation method using a limited retention vector. The limited retention vector determines whether the network increases or decreases its usage of information in external memory according to a threshold. We experimentally evaluate the robustness of a DNC implementing the proposed approach according to the size of the controller and external memory on the enwik8 LM task. When we decreased the number of weight parameters by 32.47%, the proposed DNC showed a low bits-per-character (BPC) degradation of 4.30%, demonstrating the effectiveness of our approach in language modeling tasks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.258-262
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• 2004

Storage over Ethernet (SoE) is a network storage architecture that allows direct attachment of existing ATA/ATAPI devices to Ethernet without a separate server. Unlike SAN, no server computer intervenes between the storage and the client hosts. We propose a SoE disk controller (SoEDC) amenable to low-cost, single-chip implementation that processes a simplified L3/L4 protocol and converts commands between Ethernet and ATA/ATAPI, while the rest of the complex tasks are performed by the remote hosts. Thanks to simple architecture and protocol, the SoEDC implemented on a single $4mm{\times}4mm$ chip in 0.18um CMOS technology achieves maximum throughput of 55MB/s on Gigabit Ethernet, which is comparable to that of a high-performance disk storage locally attached to a host computer.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.98-100
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• 2005

This paper, proposes concept of personal robot middleware core also called streaming layer. Based on openness and portability, the streaming layer is proposed in order to meet requirements of different kinds of applications. The streaming layer architecture provides effective management of data flows and allows integration of different systems with ease regardless software of hardware platform. With extensibility support additional features can be build in without affect to performance. Therefore, heterogeneous network support, real-time communications, embedded boards support can be easily achieved. In order to achieve high performance together with portability into different platforms, the most functions has to be implemented in C language, while critical parts, such as scheduling, priority assignment has to be made using native functions of tested platforms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.5
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• pp.2003-2021
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• 2020

Today's computer systems are widely integrated with CPU and GPU to achieve considerable performance, but energy consumption of such system directly affects operational cost, maintainability and environmental problem, which has been aroused wide concern by researchers, computer architects, and developers. To cope with energy problem, we propose a task-scheduling framework to reduce energy under performance constraint by rationally allocating the tasks across the CPU and GPU. The framework first collects the estimated energy consumption of programs and performance information. Next, we use above information to formalize the scheduling problem as the 0-1 knapsack problem. Then, we elaborate our experiment on typical platform to verify proposed scheduling framework. The experimental results show that our proposed algorithm saves 14.97% energy compared with that of the time-oriented policy and yields 37.23% performance improvement than that of energy-oriented scheme on average.

• Proceedings of the CALSEC Conference
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• 2001.08a
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• pp.379-391
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• 2001

In this paper, we presented function catalogs that Internet content transcoding system for heterogeneous client devices must offer, and, we proposed content transcoding framework architecture that is good in extensibility. This transcoding framework can accommodate each transcoder in efficient way using device capability and user preference information based on W3C's CC/PP and Wap forum's UAProf specification. This architecture offers advantages that can add developed transcoder dynamically in Plug-In form later.

• 전기의세계
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• v.26 no.1
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• pp.71-76
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• 1977

It has been expected that the 4th generation computers will be characterized for their problem adaptability. There are few techniques of implementing such a characteristic. One of the techniques that one have considered in this paper the user microprogrammable computer architecture. There are two different computer architectures that support user microprogramming. One uses the writeable control storage and another uses the main memory. The concept of utilizing writeable control storage for microprogramming was developed in 1950's and since then the most of the user microprogrammable computers produced belong to such category. The concept of utilizing the main memory for user microprogramming was first introduced by Thomas in 1973. This architecture has a strong advantage in the aspect of the system cost. In this paper, we have developed a user microprogrammable computer. The computer utilizes the main memory for user microprograms. It employs a 32 bit micro-instruction word in the form of the little encoded. The performance of the developed machine will be evaluated in the hard ware cost, programming easiness and the running time.

• International Journal of Computer Science & Network Security
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• v.21 no.12
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• pp.9-20
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• 2021

Abstraction applied in computer networking hides network details behind a well-defined representation by building a model that captures an essential aspect of the network system. Two current methods of representation are available, one based on graph theory, where a network node is reduced to a point in a graph, and the other the use of non-methodological iconic depictions such as human heads, walls, towers or computer racks. In this paper, we adopt an abstract representation methodology, the thinging machine (TM), proposed in software engineering to model computer networks. TM defines a single coherent network architecture and topology that is constituted from only five generic actions with two types of arrows. Without loss of generality, this paper applies TM to model the area of network monitoring in packet-mode transmission. Complex network documents are difficult to maintain and are not guaranteed to mirror actual situations. Network monitoring is constant monitoring for and alerting of malfunctions, failures, stoppages or suspicious activities in a network system. Current monitoring systems are built on ad hoc descriptions that lack systemization. The TM model of monitoring presents a theoretical foundation integrated with events and behavior descriptions. To investigate TM modeling's feasibility, we apply it to an existing computer network in a Kuwaiti enterprise to create an integrated network system that includes hardware, software and communication facilities. The final specifications point to TM modeling's viability in the computer networking field.

• Journal of the Korea Society of Computer and Information
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• v.28 no.9
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• pp.63-71
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• 2023

Metaverse is a modern new technology that is advancing quickly. The goal of this study is to investigate this technique from the perspective of computer vision as well as general perspective. A thorough analysis of computer vision related Metaverse topics has been done in this study. Its history, method, architecture, benefits, and drawbacks are all covered. The Metaverse's future and the steps that must be taken to adapt to this technology are described. The concepts of Mixed Reality (MR), Augmented Reality (AR), Extended Reality (XR) and Virtual Reality (VR) are briefly discussed. The role of computer vision and its application, advantages and disadvantages and the future research areas are discussed.

• Journal of Communications and Networks
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• v.14 no.6
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• pp.640-652
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• 2012

Many studies have investigated the smart grid architecture and communication models in the past few years. However, the communication model and architecture for a smart grid still remain unclear. Today's electric power distribution is very complex and maladapted because of the lack of efficient and cost-effective energy generation, distribution, and consumption management systems. A wireless smart grid communication system can play an important role in achieving these goals. In this paper, we describe a smart grid communication architecture in which we merge customers and distributors into a single domain. In the proposed architecture, all the home area networks, neighborhood area networks, and local electrical equipment form a local wireless mesh network (LWMN). Each device or meter can act as a source, router, or relay. The data generated in any node (device/meter) reaches the data collector via other nodes. The data collector transmits this data via the access point of a wide area network (WAN). Finally, data is transferred to the service provider or to the control center of the smart grid. We propose a wireless cooperative communication model for the LWMN.We deploy a limited number of smart relays to improve the performance of the network. A novel relay selection mechanism is also proposed to reduce the relay selection overhead. Simulation results show that our cooperative smart grid (coopSG) communication model improves the end-to-end packet delivery latency, throughput, and energy efficiency over both the Wang et al. and Niyato et al. models.