• Journal of Advanced Navigation Technology
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• v.18 no.2
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• pp.178-184
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• 2014

CMOS technology based on PCA is very efficient at an implementation of memory or ALU. However, there has been a growing interest in quantum-dot cellular automata (QCA) because of the limitation of CMOS scaling. In this paper, we propose a design of PCA architecture based on QCA. In the proposed PCA design, we utilize D flip-flop and XOR logic gate without wire crossing technique, and design a input and rule control switches. In experiment, we perform the simulation of the proposed PCA architecture by QCADesigner. As the result, we confirm the efficiency the proposed architecture.

• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Journal of the Korea Society of Computer and Information
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• v.21 no.12
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• pp.115-124
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• 2016

In this paper, a method to generate the extended model automatically on the critical elements in enterprise system based real time distributed architecture as well as the platform specific model(PSM) for Microsoft(MS) .NET platform is proposed. The key ideas of this method are real time distributed architecture should performed with satisfying strict constraints on life cycle of object and response time such as synchronization, transaction and so on, and .NET platform is able to implement functionalities including before mentioned by only specifying Attribute Code and maximizing advantages of MDA. In order to realize the ideas, functionalities which should be considered enterprise system development are specified and these are to be defined in Meta Model and extended UML profile. In addition, after definition of UML profile for .NET specification, by developing and applying these into plug-in of open source MDA tool, and extended models are generated automatically through this tool. Accordingly, by using proposed specification technology, the profile and tools easily and quickly reusable extended model can be generated even though low level of detailed information for functionalities which is considered in .NET platform and real time distributed architecture. In addition, because proposed profile is MOF which is basis of standard extended and applied, UML and MDA tools which observed MOF is reusable.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.93-95
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• 2021

최근, 다양한 정보의 수집 및 처리가 필요한 스마트 홈, 의료, 교통, 제조 등 여러 산업 분야에서 IoT(Internet of Things)가 많이 활용되고 있다. 특히 스마트 홈 환경에서 IoT 장치로 수집되는 정보는 민감한 개인 정보를 포함할 수 있기 때문에 특정 그룹이나 개인만이 해당 정보에 접근할 수 있도록 관리할 필요가 있다. 또한, IoT 환경에서 Blockchain 기반으로 데이터의 신뢰성을 확보하는 분산 저장소의 경우, 지연 시간의 증가 문제가 발생될 수 있기 때문에 실시간 데이터 수집에 대한 처리 속도를 향상할 방안이 필요하다. 본 논문에서는 사용자와 IoT 장치 간 생성한 그룹 ID 로 해당 그룹에 대한 접근 권한을 관리하고, Hyperledger Fabric 과 별도의 데이터베이스 운용으로 실시간성, 신뢰성을 향상할 수 있는 Hyperledger Fabric 기반 스마트 홈 Architecture 를 제안한다. 이 Architecture는 IoT 장치가 사용되는 다양한 환경에서 보안성, 실시간성, 신뢰성을 향상할 수 있을 것이다.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.1
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• pp.1196-1204
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• 2001

In this paper, a new architecture of operating software associated with the component-based method is proposed. The proposed architecture comprises 문 execution module and a decision-making module. In order to make effective development and maintenance, the execution module is divided into three components. The components are referred to as Symbol, Gateway, and Control, respectively: The symbol component is for the GUI environments and the standard interfaces; the gateway component is for the network communication and the structure of asynchronous processes; the control component is for the asynchronous processing and machine setting or operations. In order to verify the proposed architecture, and off-line version of operating software is made, and its steps are as follows; I) Make virtual execution modules for the manufacturing devices such as dual-arm robot, handling robot, CNC, and sensor; ii) Make decision-making module; iii) Integrate the modules and GUI using a well-known development tools such as Microsofts Visual Basic; iv) Execute the overall operating software to validate the proposed architecture. The proposed software architecture in this paper has the advantages such as independent development of each module, easy development of network communication, and distributed processing of resources, and so on.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.405-408
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• 2004

This paper describes an architecture information management system using XML. The purpose of the system is to manage the information stored in standard format, XML, that has many valuable properties. The proposed architecture information consists of project information, drawing information, and material information. Each information is expressed using XML and for each information, XML schema is presented in this paper. In this system, detail information of materials that exists on the supplier's homepage can be displayed when the user of the system wants to check the detail information. Also, drawings stored in STEP data can be browsed in this system. The reports of each information are prepared using XSL. The proposed system shows that XML can be used for a format to store architecture information and various functions can be implemented based on XML related standards.

• ETRI Journal
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• v.32 no.3
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• Journal of Convergence for Information Technology
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• v.7 no.2
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• pp.67-76
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• 2017

Along with shortening the life cycle of software utilization and supporting various types of user functions, the importance of software architecture development has been emphasized recently. If a software architecture is developed flexibly and reliably for expansion to support new functionality, it can quickly cope with new market demands. This paper proposes an architecture design method based on design recovery of open source software to reuse the software in the development of sustainable software system. When using open source software to develop a software system based on software architecture, we can develop a software system rapidly and also can improve the reliability of the system because we use the already proven open source software in the development.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.1
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• pp.41-47
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• 2008

This paper presents a new digit level LSB-first multiplier for computing a modular multiplication and a modular squaring simultaneously over finite field GF($2^m$). To derive $L{\times}L$ digit level architecture when digit size is set to L, the previous algorithm is used and index transformation and merging the cell of the architecture are proposed. The proposed architecture can be utilized for the basic architecture for the crypto-processor and it is well suited to VLSI implementation because of its simplicity, regularity, and concurrency.