• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.145-149
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• 2011

Recently, as the design of a system gets larger and more complex, functional verification method based on system-level becomes more important. The verification of a functional block mainly uses BFM(bus functional model). The larger the burden on functional verification is, the more the importance of configuring a proper verification environment increases rapidly. SystemVerilog unifies hardware design languages and verification languages in the form of extensions to the Veri log HDL. The processing of design description, function simulation and verification using same language has many advantages in system development. In this paper, we design DUT that is composed of AMBA bus and function blocks using SystemVerilog and verify the function of DUT in verification environment using layered testbench. Adaptive FIR filter and Booth's multiplier are chosen as function blocks. We confirm that verification environment can be reused through a minor adaptation of interface to verify functions of other DUT.

• Journal of the Korean Regional Science Association
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• v.6 no.2
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• pp.123-147
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• 1990

This paper examines the changing geography of producer service industries in the 1980s. The foci of this study are to analyze the regional distribution of each producer services, and to reveal the spatial linkage of producer services. Further this paper asserts the potential role of producer services for reducing the potential endogenous development in the periphery. During the 1981-86 period, producer service industries grew more rapidly than other service sectors and manufacturing sector. The main reason of the raid growth of producer services is attributable to an increase in demand for intermediate services from manufacturing firms. In order to compete an increasingly complex business environment, firms have expanded the amount of effort devoted to activities such as planning, coordination and control, and consequently have increased their use of producer services. The most distinctive feature of the location of producer services is spatial concentration into Seoul and surrounding region. Especially the degree of the concentration o business services into the Capital Region has been accelerating during the 1990s. The pattern of employment growth and regional distribution of producer services show a clear core / periphery disparity. Much of the regional inequality in producer services is largely due to variation in demand associated with the pattern of corporation headquarters with the pattern of corporation headquarters and branch plants location with large manufacturing firms. The analysis of spatial division of labor reflects that producer services are related to the location of headquarters in manufacturing industry. Headquarters in manufacturing firms and business service firms tend to cluster each other. Most of the headquarters spatially separated from branch offices are clustered heavily in Seoul. Especially headquarters of business services and insurance services are overwhelmingly concentrated into Seoul. The firms whose headquarters are located in Seoul have a linkage pattern on a nationwide scale. It is viewed have little potential for generating local multiplier effects and regional development. In the light of the result of this study, producer services are not likely to disperse soon to peripheral regions. Consequently the absence of policies directed at enhancing producer sevice in the periphery, concentration tendency would continue to reinforce the core's dominance at the expense of peripheral regions. From a regional perspective, the quality of a region's producer service sector is a key determinant of economic growth, since manu industrial location decisions are influenced by the differential availability of producer services among regions. Poor performance of producer services in peripheral regions seemed to be linked to the region's manufacturing base. Low-wage, standardized branch plants are not likely to induce the growth in knowledge intensive services associated with high-technology corporate headquarters. Producer services may help to create and attract new business including manufacturing firms, and also to enhance the productivity and competitiveness of local firms. Therefore the provision of service producing activities would be lead not only to generate and retain endogenous development but also to attract external firms, especially small and medium sized firms which have a lower propensity of internalized services. Hence, it may be more efficient to create and expanse new locally owned producer services rather than to attract branch plants of mult-locational firms in order to make indigenous economic development.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.