• 제목/요약/키워드: complete synchronization

검색결과 19건 처리시간 0.023초

Low Power Time Synchronization for Wireless Sensor Networks Using Density-Driven Scheduling

  • Lim, HoChul;Kim, HyungWon
    • Journal of information and communication convergence engineering
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    • 제16권2호
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    • pp.84-92
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    • 2018
  • For large wireless sensor networks running on battery power, the time synchronization of all sensor nodes is becoming a crucial task for waking up sensor nodes with exact timing and controlling transmission and reception timing. However, as network size increases, this synchronization process tends to require long processing time consume significant power. Furthermore, a naïve synchronization scheduler may leave some nodes unsynchronized. This paper proposes a power-efficient scheduling algorithm for time synchronization utilizing the notion of density, which is defined by the number of neighboring nodes within wireless range. The proposed scheduling algorithm elects a sequence of minimal reference nodes that can complete the synchronization with the smallest possible number of hops and lowest possible power consumption. Additionally, it ensures coverage of all sensor nodes utilizing a two-pass synchronization scheduling process. We implemented the proposed synchronization algorithm in a network simulator. Extensive simulation results demonstrate that the proposed algorithm can reduce the power consumption required for the periodic synchronization process by up to 40% for large sensor networks compared to a simplistic multi-hop synchronization method.

IEEE 1588 표준을 지원하는 이기종 분산 네트워크 환경에서 시간 동기화를 위한 PTP 알고리즘 기반의 어플리케이션 프레임워크 개발 기법 (Support the IEEE 1588 Standard in A Heterogeneous Distributed Network Environment PTP for Time Synchronization Algorithms Based Application Framework Development Method)

  • 조경래
    • 디지털산업정보학회논문지
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    • 제9권3호
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    • pp.67-78
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    • 2013
  • In this paper, We proposed an development method of application framework for using the precision time protocol(PTP) based on physical layer devices to synchronize clocks across a network with IEEE1588 capable devices. The algorithm was not designed as a complete solution across all conditions, but is intended to show the feasibility of such a for the PTP(Precision Time Protocol) based on time synchronization of heterogeneous network between devices that support in IEEE 1588 Standard application framework. With synchronization messages per second, the system was able to accurately synchronize across a single heavily loaded switch. we describes a method of synchronization that provides much more accurate synchronization in systems with larger networks. In this paper, using the IEEE 1588 PTP support for object-oriented modeling techniques through the 'application framework development Development(AFDM)' is proposed. The method described attempts to detect minimum delays, or precision packet probe and packet metrics. The method also takes advantage of the Tablet PC(Primary to Secondary) clock control mechanism to separately control clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of the clock. We verifying the performance of PTP Systems through experiments that proposed method.

Analysis, Control, and Synchronization of a 3-D Novel Jerk Chaotic System with Two Quadratic Nonlinearities

  • VAIDYANATHAN, SUNDARAPANDIAN
    • Kyungpook Mathematical Journal
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    • 제55권3호
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    • pp.563-586
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    • 2015
  • In this research work, a seven-term 3-D novel jerk chaotic system with two quadratic nonlinearities has been proposed. The basic qualitative properties of the novel jerk chaotic system have been described in detail. Next, an adaptive backstepping controller is designed to stabilize the novel jerk chaotic system with two unknown parameters. Moreover, an adaptive backstepping controller is designed to achieve complete chaos synchronization of the identical novel jerk chaotic systems with two unknown parameters. MATLAB simulations have been shown in detail to illustrate all the main results developed for the 3-D novel jerk chaotic system.

Extending Network Domain for IEEE1394

  • Lee, Seong-Hee;Park, Seong-Hee;Choi, Sang-Sung
    • 한국정보기술응용학회:학술대회논문집
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    • 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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    • pp.177-178
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    • 2005
  • Wireless 1394 over IEEE802.15.3 must allow a data reserved for delivery over a wired 1394 network to be delivered over an IEEE802.15.3 wireless network through bridging IEEE 1394 to IEEE802.15.3. Isochronous transfers on the 1394 bus guarantee timely delivery of data. Specifically, isochronous transfers are scheduled by the bus so that they occur once every $125\;{\mu}s$ and require clock time synchronization to complete the real-time data transfer. IEEE1394.1 and Protocol Adaptation Layer for IEEE1394 over IEEE802.15.3 specify clock time synchronization for a wired 1394 bus network to a wired 1394 bus network and wireless 1394 nodes, which are IEEE802.15.3 nodes handling 1394 applications, over IEEE802.15.3. Thus, the clock time synchronizations are just defined within a homogeneous network environment like IEEE1394 or IEEE802.15.3 until now. This paper proposes new clock time synchronization method for wireless 1394 heterogeneous networks between 1394 and 802.15.3. If new method is adopted for various wireless 1394 products, consumer electronics devices such as DTV and Set-top Box or PC devices on a 1394 bus network can transmit real time data to the AV devices on the other 1394 bus in a different place via IEEE 802.15.3.

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소규모 무선 네트워크에 적합한 중앙제어 방식의 DESYNC 개선 방안 (A Centralized DESYNC Scheme in Small-Scale Wireless Networks)

  • 이남권;현상현;이제율;이규원;양동민
    • 한국정보통신학회논문지
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    • 제19권3호
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    • pp.731-740
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    • 2015
  • 최근 기기간 통신에 따른 소규모 네트워크에 적합한 통신 방법들에 대한 관심이 급증하면서 수요가 증가하고 있다. 소규모 네트워크의 기본적 시스템은 TDMA(Time Division Multiple Access)방식이 사용될 수 있다. 하지만 TDMA는 동기화 방식이 복잡하고 추가 장비가 필요하며 비용적인 측면에서 비효율 적이다. 때문에 본 논문에서는 DESYNC(DESYNChronization)를 이용하여 소규모 네트워크에 적합한 동기화 방법을 제안한다. 기존 DESYNC는 동기화 완료까지의 시간이 걸리고 지연시간을 보장하지 않는다. 본 논문에서는 DESYNC 알고리즘을 개선하여 BC(Bridge Count)-DESYNC를 제안한다. BC-DESYNC는 통신 범위를 초과한 노드들 사이에 CU(Central Unit)을 배치하여 중앙제어장치 기능을 통해 노드들의 통신이 가능하도록 하며, Mimic DESYNC와 C-DESYNC를 이용하여 동기화 상태 완료 시간을 보장한다.

삼상제어력유기 입상 제어회로의 디지털화 (Digitalization of the phase Control Circuit of a three-phase Controlled Rectifier)

  • 박민호;정승기;김기택
    • 대한전기학회논문지
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    • 제36권2호
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    • pp.107-113
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    • 1987
  • A complete design of a new digital control circuit for a three-phase controlled rectifier is presented. The circuit consists of a gating signal generating ROM, down counter and adder. Proposed scheme is simple and quite adequate to the microprocessor-based digitally controlled systems. The basic principle and operation characteristics of the circuit are described and experimental-results show good dynamic performance. Synchronization problem with noisy reference is also discussed. The basic phylosophy developed can be extended to the other phase control system, e.g., cycloconverters, ac voltoge controllers, etc.

단일홉 무선 애드혹 네트워크에서 단순 TDMA 시스템을 위한 DESYNC 알고리즘 개선 방안 (An Enhanced DESYNC Scheme for Simple TDMA Systems in Single-Hop Wireless Ad-Hoc Networks)

  • 현상현;이제율;양동민
    • 정보처리학회논문지:컴퓨터 및 통신 시스템
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    • 제3권9호
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    • pp.293-300
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    • 2014
  • TDMA(Time Division Multiple Access)는 무선 네트워크에서 한정된 주파수 대역을 일정한 크기의 시간 단위인 슬롯으로 분할하고 사용자가 할당된 슬롯을 이용하여 통신할 수 있는 채널 접속 기술이다. TDMA에 사용되는 기술에 따라 동기와 비동기 방식으로 나눌 수 있다. TDMA의 동기화 과정은 복잡하고, 추가 장비가 필요할 수 있기 때문에 소규모 네트워크에 적합하지 않다. 반면, 비동기 방식의 DESYNC에서는 전역 클록(global clock)이나 기반 시설 도움 없이 동기화를 이룰 수 있다. 하지만 DESYNC는 동기화 완료하는 데 제법 시간이 걸리고, 소요되는 최대 지연 시간이 얼마인지 보장하지 못한다. 그래서 본 논문에서는 소규모 네트워크에 적합한 경량 동기화 기법인 C-DESYNC를 제안한다. C-DESYNC는 참가 하는 노드의 주기 시작 정보를 가지고 있는 GP (Global Packet) 신호와 노드들의 firing 개수를 이용하여 노드의 개수를 파악하고, 이 정보를 이용하여 동기화를 이룬다. 제시하는 알고리즘은 기존의 동기화 방식의 TDMA 기법에 비해 간단하여 비용 측면에서도 효율적이며, 동기화 완료시까지 걸리는 최대 지연시간을 보장한다. 시뮬레이션 결과를 통해서 C-DESYNC는 참가 노드 개수에 관계없이 오직 3 주기 내에 동기화 완료를 보장하는 것을 보여준다.

DOS 환경 로봇제어기용 실시간 운영체계를 위한 멀티태스킹 커널의 설계및 구현 (A design and implementation of DOS-based multitasking Kernel of the real-time operating systems for robot controller)

  • 장호;이기동
    • 제어로봇시스템학회논문지
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    • 제3권4호
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    • pp.373-380
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    • 1997
  • In order to implement the real-time operating systems for robot controller, this paper proposes a systematic method for implementing the real-time kernel under the DOS environment. So far, we designed the robot control software and its own operating system simultaneously. Though robot operating systems have simple structure, it allows the developer to have a surplus time and effort to implement complete robot systems. In addition to this, in most cases of this type, operating systems does not support multitasking function, thus, low level hardware interrupts are used for real-time execution. Subsequently, some kinds of real-time tasks are hard to implement under this environment. Nowadays, the operating systems for robot controller requires multitasking functions, intertask communication and task synchronization mechanism, and rigorous real-time responsiveness. Thus, we propose an effective and low costs real-time systems for robot controller satisfying the various real-time characteristics. The proposed real-time systems are verified through real implementation.

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Bit Decision 윈도우를 이용한 Noncoherent IR-UWB 수신기의 심벌 동기에 관한 연구 (Symbol Synchronization Technique using Bit Decision Window for Non-Coherent IR-UWB Systems)

  • 이순우;박영진;김관호
    • 대한전자공학회논문지TC
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    • 제44권2호
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    • pp.15-21
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    • 2007
  • 본 논문에서는 Impulse-radio-based Ultra Wideband (IR-UWB)를 이용한 에너지 검출 기반의 비동기 수신기에서 저사양의 ADC와 간단한 디지털 회로 만으로 이루어진 심벌 동기 획득(acquisition) 및 심벌 동기 추적(tracking) 방식을 제안한다. 기존의 심벌 동기 방식이 정확한 심벌 동기 '시점을 찾는 것에 초점을 맞추었다면, 제안하는 방식은 심벌 동기 '구간'을 찾아 그 구간 내에서 데이터를 판단함으로써 하드웨어 복잡성을 낮추었고, 전력 소모를 줄였다. 이를 위해 심벌 동기 구간에 해당하는 BDW (Bit Decision Window)를 정의하고 SNR(Signal to Noise Ratio), 하드웨어 자원 및 BDW의 크기와 BER (Bit Error Rate)와의 관계를 분석하였다. 주어진 SNR과 하드웨어 자원으로 BER을 최소화하기 위한 BDW의 크기를 구한다. 제안한 알고리즘은 실제 임펄스 채널 특성을 고려하여 모의실험을 통하여 검증하였다.

Effects of incubation temperature on the embryonic viability and hatching time in Russian sturgeon (Acipenser gueldenstaedtii)

  • Kim, Eun Jeong;Park, Chulhong;Nam, Yoon Kwon
    • Fisheries and Aquatic Sciences
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    • 제21권9호
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    • pp.23.1-23.8
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    • 2018
  • Background: Russian sturgeon (Acipenser gueldenstaedtii) is an emerging candidate species in the Korean aquaculture domain owing to its highly valued caviar. Although the embryonic development of this species was previously described, the complete image data on the morphological differentiation of developing embryos have not been yet fully available. Further, with the viewpoint of larval production in hatchery, the effects of temperature on embryonic viability and the temporal window of hatching event have not been extensively studied. Hence, the objective of this study was to provide a complete set of photographic image data on the embryogenesis and also to examine the effects of incubation temperatures on embryonic viability and hatching event in farm-bred Russian sturgeon. Results: Typical characteristics of embryonic development including uneven, holoblastic cleavages with unequal blastomeres, followed by the formation of germ layer, neurulation, and organogenesis until hatching, were documented. Under different temperature conditions (12, 16, or $20^{\circ}C$), viability of embryos incubated at $12^{\circ}C$ was significantly lower as relative to those of 16 and $20^{\circ}C$ incubated embryos. Hatchability of embryos was higher, and the timing of hatching event was more synchronized at $20^{\circ}C$ than at 12 and $16^{\circ}C$. Conclusion: Data from this study suggest that the incubation of Russian sturgeon embryos at $20^{\circ}C$ would be desirable in the hatchery practice with respect to the good hatchability of embryos and the synchronization of hatching events. Additionally, the updated image data for complete embryonic development could be a useful reference guide for not only developmental researches but also artificial propagation of Russian sturgeon in farms.