• 전기학회논문지P
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• 제57권3호
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• pp.291-295
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• 2008

We have developed an evaluation technique for ratio errors of current transformer (CT) comparator by using the precise standard capacitors. By applying this technique for equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured ratio errors in the CT comparator. Thus we can evaluate ratio errors of CT comparator by comparing the calculated and measured ratio errors. Because this method requires only the standard capacitors, it is simple and easy method to reliability and accuracy maintenance of CT comparator. The method was applied to CT comparator under test with the ratio error ranges of $0{\sim}{\pm}10%$. The ratio error of the CT comparator under test theoretically obtained in this method are consistent with that measured for same CT comparator under test by using wide ratio error CT within an estimated expanded uncertainty (k = 2) in the overall ratio error ranges.

• 전기학회논문지P
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• 제57권4호
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• pp.437-443
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• 2008

We have developed an evaluation technique for both ratio error and phase displacement of current transformer (CT) comparator by using the precise standard capacitors and resistors. By applying this technique to equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured ratio errors (or phase displacements) in the CT comparator. Thus we can evaluate ratio errors and phase displacement of CT comparator by comparing the calculated and measured ratio errors (or phase displacements). The method was applied to CT comparator under test with the ratio errors and phase displacement ranges of $0{\sim}{\pm}10%$ and $0{\sim}{\pm}7.5$ crad, respectively. Finally we have compared the ratio error and phase displacement of the CT comparator obtained in this method with specifications of two companies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.2032-2033
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• 2008

We have developed an evaluation technique for phase displacement of current transformer (CT) comparator by using the precise standard capacitors and resistors. By applying this technique for equivalent circuit of CT comparator evaluation system, we can obtain the calculated and measured phase displacement in the CT comparator. Thus we can evaluate phase displacement of CT comparator by comparing the calculated and measured phase displacement. The method was applied to CT comparator under test with the phase displacement ranges of $0{\sim}{\pm}7.5$ crad. Finally we have compared the phase displacement of the CT comparator under test theoretically obtained in this method with the specification.

• 전기학회논문지P
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• 제57권4호
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• pp.412-416
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• 2008

We have developed the calibration technique of the VT comparator using nonreactive standard resistors, which evaluates both accuracy and linearity of the VT comparator by comparing experimental values with theoretical values. The correction values of VT comparator obtained by using both our method and wide ratio error VT are consistent within the expanded uncertainty. Furthermore the specification for ratio error of VT comparator have been revaluated.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.1-9
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• 2009

본 논문에서는 MOS 트랜지스터가 FN 스트레스에 의해 문턱전압이 이동하는 현상을 이용하여 비교기 회로의 옵셋을 제거하는 방법을 소개하고, 이를 비교기 회로의 성능개선에 적용해 보인 결과를 보인다. 옵셋이 성능을 저하시키는 대표적인 회로인 DRAM의 비트라인 감지증폭기에 적용하여 옵셋을 제거하는 방법을 설명하고, 테스트 회로를 제작 및 측정하는 실험을 통해서 이를 검증한다. 본 방식은 래치구조가 포함된 모든 형태의 비교기에 적용가능하며, 스트레스-패킷이라고 명명한 형태의 스트레스 바이어스 시퀀스를 통해 다양한 초기 옵셋값을 가지는 많은 숫자의 비교기가 동시에 거의 제로 옵셋으로 수렴할 수 있음을 보인다. 또한 이 방법을 비교기 회로에 적용하는데 있어서 고려해야 할 몇 가지 신뢰도 조건에 대해서도 고찰한다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권2호
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• pp.66-70
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• 2005

Linearity of ratio error of instrument transformer comparator has been tested using wide ratio error voltage transformer(VT) with the ratio errors in the range of -3 ％ to 3 ％. The technique is the method for evaluation of the linearity for instrument transformer comparator by comparing both the theoretical and experimental values in wide ratio error VT. The developed method has been successfully applied for calibration and correction in instrument transformer comparator belonging to industry.

• 한국철도학회:학술대회논문집
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• 한국철도학회 1998년도 추계학술대회 논문집
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• pp.270-279
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• 1998

This paper presents the design of self-checking comparator using the time diversity and the application to 8 bit CPU for the implementation of fault tolerant computer system. this self-checking comparator was designed with the different time Points in which temporary faults were raised by electrical noise between duplicated functional blocks. also this self-checking comparator was simulated in the method of the fault injection using 4 bit shift register counter. we designed the duplicated Emotional block and the self-checking comparator in the single chip using the Altera EPLD and could verify the reliability and the fault detection coverage through the modeling of temporary faults ,especially intermittent faults. at the results of this research, the reliability and the fault detection coverage were implemented through the self-checking comparator using the time diversity.

• 전기학회논문지P
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• 제57권3호
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• pp.279-284
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• 2008

We have developed two absolute evaluation technology of inductor using current transformer (CT) comparator. One is the method that the reactance of inductor is obtained by analysing the equivalent circuit of CT with inductor connected to series at secondary terminal of CT. The other is the method that the reactance of inductor is obtained by comparing phase displacement of current flowing on inductor by using CT comparator. These technologies have the advantage to apply up to rated current and voltage of inductor. The method was applied to inductors under test in the range of $100 {\mu}H{\sim}1\;H$. The inductance of the inductor under test obtained in this study are consistent with those measured by LCR meter using the same inductor within an expanded uncertainty (k = 2) in the overall range of inductance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1035-1037
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• 2001

This paper presents an improved hys- teresis current control method for three-phase PWM power inverters using 3-level comparator. Hysteresis current controller using 3-level comparator has an advantage of constant switching frequency compared with conventional hysteresis current controller. However, this method has disadvantage that the longer sampling period, the larger current error because the switching is performed without considering current error magnitude of each phase. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous hysteresis current control method.

• Nuclear Engineering and Technology
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• 제18권2호
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• pp.85-91
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• 1986

원자로 중성자 방사화 분석법으로 다중 원소들을 분석하기 위한 단일 비교체법을 그에 따른 오차와 함께 조사하였다. 각 시료의 조사 위치에서 스펙트럴 지수는 Au와 Co 두개의 모니터를 이용하여 결정하였으며 이중 한개는 단일 비교체로 사용하였다 18개 원소에 대하여 이 방법에 사용된 핵 자료의 불확실도를 조사하였으며, 이 값들에 의한 분석 결과의 오차는 6% 이하이었다. 4개의 USGS 표준시료의 분석 결과는 USGS에서 평가한 분석결과와 15%의 편차 이내에서 잘 일치하였다.