• Title/Summary/Keyword: collect feedback circuit

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An Efficient Bias Circuit of Discrete BJT Component for Hearing Aid (보청기를 위한 개별 BJT 소자의 효과적인 바이어스 회로)

  • 성광수;장형식;현유진
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.16-23
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    • 2003
  • In this paper, we propose an efficient bias circuit of discrete BJT component for hearing aid. The collector feedback bias circuit, widely used for the hearing aid, has a resistor for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor to the collector feedback bias circuit between base and power supply which is $\beta$ times target than the collector resistor. Thus. we can change amplifier gain without changing DC bias point, and reduce power noise gain about 18.5% compare to that of tile previous circuit in the simulation.

Performance Analysis of 403.5MHz CMOS Ring Oscillator Implemented for Biomedical Implantable Device (생체 이식형 장치를 위해 구현된 403.5MHz CMOS 링 발진기의 성능 분석)

  • Ferdousi Arifa;Choi Goangseog
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.19 no.2
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    • pp.11-25
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    • 2023
  • With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.