• Journal of information and communication convergence engineering
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• 제3권3호
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Journal of Communications and Networks
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• 제8권1호
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Journal of information and communication convergence engineering
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• 제8권3호
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• pp.339-342
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• 2010

An iris image pattern positioning with preserved edge detector, ring zone and clock zone, frequency distribution and overlay matching is presented in this paper. Edge detector is required to be powerful and detail. That is proposed by overlaying Canny with LOG (CLOG). The two reference patterns are made from allocating each gray level on the clock zone and ring zone respectively. The normalized target image is overlaid with the clock zone reference pattern and the ring zone pattern to extract overlapped number, and make a matched frequency distribution to look through a symptom and position of human organ and tissue. The iterating experiments result in the ring and clock zone positioning evaluation.

• Journal of Information Display
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• 제10권1호
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• pp.37-44
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• 2009

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

• Journal of Positioning, Navigation, and Timing
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• 제5권3호
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• pp.137-144
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• 2016

In this paper, the performance of ranging measurement, which is generated using two receiver clock offsets in one receiver, was analyzed. A spoofer transmits a counterfeited spoofing signal which is similar to the GPS signal with hostile purposes, so the same tracking technique can be applied to the spoofing signal. The multi-correlator can generate two receiver clock offsets in one receiver. The difference between these two clock offsets consists of the path length from the spoofer to the receiver and the delay of spoofer system. Thus, in this paper, the ranging measurement was evaluated by the spoofer localization performance based on the time-of-arrival (TOA) technique. The results of simulation and real-world experiments show that the position and the system clock offset of the spoofer could be estimated successfully.

• 전기학회논문지
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• 제61권11호
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• pp.1695-1699
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• 2012

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

• 한국지능시스템학회:학술대회논문집
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• 한국지능시스템학회 2008년도 춘계학술대회 학술발표회 논문집
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• ETRI Journal
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• 제33권6호
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• pp.841-848
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• 2011

A signal-to-noise ratio (SNR) enhancement algorithm using multiple chirp symbols with clock drift is proposed for accurate ranging. Improvement of the ranging performance can be achieved by using the multiple chirp symbols according to Cramer-Rao lower bound; however, distortion caused by clock drift is inevitable practically. The distortion induced by the clock drift is approximated as a linear phase term, caused by carrier frequency offset, sampling time offset, and symbol time offset. SNR of the averaged chirp symbol obtained from the proposed algorithm based on the phase derotation and the symbol averaging is enhanced. Hence, the ranging performance is improved. The mathematical analysis of the SNR enhancement agrees with the simulations.

• Journal of Information Display
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• 제12권1호
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.