• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.336-344
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• 2017

This paper presents the three-port DC-DC converter modeling and controller design procedure, which is part of the solid-state transformer (SST) to interface medium voltage AC grid to bipolar DC distribution network. Due to the high primary side DC link voltage, the proposed converter employs the three-level neutral point clamped (NPC) topology at the primary side and 2-two level half bridge circuits for each DC distribution network. For the proposed converter particular structure, this paper conducts modeling the three winding transformer and the power transfer between each port. A decoupling method is adopted to simplify the power transfer model. The voltage controller design procedure is presented. In addition, the output current sharing controller is employed for current balancing between the parallel-connected secondary output ports. The proposed circuit and controller performance are verified by experimental results using a 30 kW prototype SST system.

• ETRI Journal
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• v.33 no.6
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• Journal of Electrical Engineering and Technology
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• v.9 no.4
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• pp.1296-1308
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• 2014

This paper presents a new zero voltage switching (ZVS) converter for medium power and high input voltage applications. Three three-level pulse-width modulation (PWM) circuits with the same power switches are adopted to clamp the voltage stress of MOSFETs at $V_{in}/2$ and to achieve load current sharing. Thus, the current stresses and power ratings of transformers and power semiconductors at the secondary side are reduced. The resonant inductance and resonant capacitance are resonant at the transition interval such that active switches are turned on at ZVS within a wide range of input voltage and load condition. The series-connected transformers are adopted in each three-level circuit. Each transformer can work as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer. Thus, no output inductor is needed at the secondary side. Three center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Compared with the conventional parallel three-level converters, the proposed converter has less switch counts. Finally, experiments based on a 1.44kW prototype are provided to verify the operation principle of proposed converter.

• Journal of Power Electronics
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• v.13 no.4
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• pp.679-691
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• 2013

High-power electromagnetic transmitter power supplies are an important part of deep geophysical exploration equipment. This is especially true in complex environments, where the ability to produce a highly accurate and stable output and safety through redundancy have become the key issues in the design of high-power electromagnetic transmitter power supplies. To solve these issues, a high-frequency switching power cascade based emission power supply is designed. By combining the circuit averaged model and the equivalent controlled source method, a modular mathematical model is established with the on-state loss and transformer induction loss being taken into account. A triple-loop control including an inner current loop, an outer voltage loop and a load current forward feedback, and a digitalized voltage/current sharing control method are proposed for the realization of the rapid, stable and highly accurate output of the system. By using a new algorithm referred to as GAPSO, which integrates a genetic algorithm and a particle swarm algorithm, the parameters of the controller are tuned. A multi-module cascade helps to achieve system redundancy. A simulation analysis of the open-loop system proves the accuracy of the established system and provides a better reflection of the characteristics of the power supply. A parameter tuning simulation proves the effectiveness of the GAPSO algorithm. A closed-loop simulation of the system and field geological exploration experiments demonstrate the effectiveness of the control method. This ensures both the system's excellent stability and the output's accuracy. It also ensures the accuracy of the established mathematical model as well as its ability to meet the requirements of practical field deep exploration.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.3
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• pp.20-28
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• 2002

This paper describes the time sharing type high frequency resonant inviter can be used as power of induction heating. This closed inverter can be obtained output frequency three times than switching frequency by composing three unit inviter of conventional Half-Bridge serial resonant inverter in parallel with input power source also, this reduce switching loss because it has ZVS function. The analysis of the proposed circuit is generally described by using the normailized proposed parameters. The principle of basic operating and the its charasteristics are extimated by the parameters such as switching frequency($\mu$), the variation of Phase angle($\phi$) of Phase-shift. Experimental results are presented to verify theoretical discussion. This preposed inverter will be able to be prastically used as a power supply in various fields as induction, heating application, DC-DC converter etc.

• Journal of Power Electronics
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• v.15 no.3
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• pp.652-659
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• 2015

This paper presents a new hybrid soft switching dc-dc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two sub-converters sharing two power switches. One is a three-level PWM converter and the other is a LLC converter. The LLC converter and the three-level converter share the lagging-leg switches and extend the zero-voltage switching (ZVS) range of the lagging-leg switches from nearly zero to full load since the LLC converter can be operated at f_sw (switching frequency) $\approx$ f_r (series resonant frequency). A passive snubber is used on the secondary side of the three-level converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44kW prototype circuit.

• Journal of KIISE:Software and Applications
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• v.37 no.8
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• pp.647-652
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• 2010

Esterel is an imperative synchronous language well-adapted to control-intensive systems. When an Esterel program is translated to a circuit, the synchronizer of a parallel statement may be executed more than once in a clock; the synchronizer is called schizophrenic. Existing compilers cure the problems of schizophrenic parallel synchronizers using logic duplications. This paper proposes the conditions under which a synchronizer causes no problem in circuits when it is executed more than once in a clock. In addition we design a detection algorithm based on those conditions. Our algorithm detects schizophrenic parallel synchronizers that have to be duplicated in Esterel source codes so that compilers can save the size of synthesized circuits

• Journal of Power Electronics
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• v.16 no.2
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• Journal of Power Electronics
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• v.12 no.2
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• pp.249-257
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• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.24-25
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• 2017

In this paper, a low cost bridgeless interleaved power factor correction topology for electric vehicle charger application is proposed. With the proposed topology the number of switches, inductors, current sensors and associated circuits can be reduced, thereby reducing the cost of the system as compared to the conventional bridgeless PFC circuit. The reduced input current ripple by the proposed interleaved topology makes it suitable for high power applications such as electric vehicle chargers since it can reduce the size of the inductor core and the Electro Magnetic Interference (EMI) problem. In the proposed topology only one current sensor is required. All the boost inductor currents can be reconstructed by sampling the output current and used to control the input current. Therefore the typical problem caused by the unequal current gain of each current sensor inherently does not exist in the proposed topology. In addition the current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. The performance of the proposed converter is verified by the experimental results with a prototype of 6.6kW bridgeless interleaved PFC circuit.