• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.363-364
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• 2016

In this paper, a novel bridgeless interleaved power factor correction circuit with single current sensor is proposed. The proposed control strategy requires only one current sensor for the interleaved bridgeless PFC. By sampling the output current, all the boost indictor currents can be calculated and used to control the input current according to the input voltage. The reduced number of current sensors and associated feedback circuits helps reduce the cost of system. The problem caused by the unequal current gain between current sensors inherently does not exist in the proposed topology. Thus, current sharing between converters can be achieved more accurately and the high frequency distortion is decreased. In addition, the proposed technique can be applied to the other kinds of interleaved PFC topologies. Performance of the proposed control strategy is verified by the experimental results with 6.6kW bridgeless interleaved PFC circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.291-295
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• 1989

The conventional Optimized Injection Method is a good control technique but can't be applied to 3-phase a.e. line. In this paper, a new technique, Time-sharing Method based on basic principle of conventional Optimized Injection Method is introduced to hold the independence of each phase, and the structure of power circuit is improved to realize the new control method. By this scheme it is possible to simplify the control circuit and power circuit. The characteristic of the new control method are investigated and compared with conventional Optimized Injection Method by computer simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 정보 및 제어부문
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• pp.237-239
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• 2005

In this paper PLC Power Circuit with Hot-Swap Function is proposed for stable power supplies. The power modules of the proposed devices are implemented by CRM flyback converter using new synchronous rectifier circuit for high efficiency. By a variable switching frequency controller, this converter is operated with a reduced turn-on switching loss. Also, the load current in these power modules are shared by auto master / slave method using Outer loop. The proposed devices are analyzed in detail and optimized for high performance. Experimental results for a 100W power module at the variable switching frequency of 30$^{\sim}$70kHz were obtained to show the performance of the proposed device.

• Journal of Power Electronics
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• 제12권5호
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• pp.699-707
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• 2012

This paper proposes a single-stage half-bridge electronic ballast with a high power factor using only a single coupled inductor. Compared to conventional high power factor electronic ballasts, the proposed ballast is a simpler circuit with a low cost and a high reliability. The proposed ballast is made up of a power-factor-correction (PFC) circuit and a self-oscillating class-D inverter. The PFC and inverter stages of the proposed ballast are simplified by sharing only a single coupled inductor and two common switches. The proposed PFC circuit can achieve a high power factor and low voltage stresses of the switches. A saturable transformer in the self-oscillating class-D inverter determines the switching frequency of the ballast. Experimental results obtained on a 30W fluorescent lamp are discussed.

• Smart Structures and Systems
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• 제14권6호
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1534-1536
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• 2005

A DC-DC converter is being widely used for various household appliances and for industry applications. The DC-DC converter is powered from single battery, and the voltage is varied according to the purpose. In the vehicle, various accessories whose electric power is different are being used. Thus, plural number of DC-DC converter should be provided, so these situations bring complicated circuits, and accordingly, higher cost. Under such backgrounds, in this paper, we propose a novel buck-boost chopper circuit with simply configuration which can supply to two or more different output loads. The propose chewer circuit can control output voltages by controlling duty ratio by using typically two switching devices, which is composed by single boost-switch and single buck-switch. The output voltage can be controlled widely. A few modified circuits developed from the fundamental circuit are represented including the general multi-load circuit. And all this merits and appropriateness was proved by computer simulation and experience.

• 전자공학회논문지
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• 제53권12호
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• pp.50-56
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• 2016

이 논문은 UHD 영상을 지원하는 멀티 디코더 용 인트라 예측 회로의 구조와 설계를 제안하고 있다. 제안된 회로는 가장 최신의 비디오 압축 표준인 HEVC뿐만 아니라 H.264도 지원한다. 이 회로는 기본적인 인트라 예측 기능이외에 추가적으로 H.264 표준에 정의되어 있는 참조 샘플 필터 연산과 HEVC 표준에 정의되어 있는 약한 참조 샘플 필터 및 강한 참조 샘플 필터 연산을 처리하는 기능도 갖고 있다. 공통적인 연산부와 내부 저장소를 공유함으로써 회로의 크기를 감소시켰으며, 병렬 연산을 통하여 성능을 향상시켰다. 제안된 회로는 Verilog HDL(Hardware Description Language)을 이용하여 RTL(Register Transfer Level)로 기술하였으며, Cadence의 NC-Verilog를 이용하여 기능을 검증하였다. RTL 회로를 Synopsys의 Design Compiler 및 130nm 표준 셀 라이브러리를 이용하여 합성하였다. 합성된 게이트 수준 회로는 69,694개의 게이트로 구성되며, 최대 동작주파수 157MHz에서 4K-UHD HEVC 영상을 초당 100 ~ 280 프레임의 속도로 처리한다.

• 한국광학회지
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• 제27권6호
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• pp.212-217
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• 2016

연결 지향적 데이터 경로 서비스는 운영중인 데이터 경로에 문제가 생겼을 경우, 이의 인지와 변경을 제한된 시간 내에 끝내야 한다. 서비스 중인 데이터 경로에 이상이 있을 경우 계속해서 데이터 유실이 발생하기 때문에, 경로 서비스를 제공하는 데이터 스위칭 시스템은 문제의 경로를 신속하게 정상 경로로 전환해야 한다. 시스템의 신속한 경로 전환을 위해서는 문제 (이벤트)의 인지와 공유와 처리 과정이 신속하게 끝나야 한다. 본 논문에서는 테라비트 광-회선-패킷 통합 스위칭 시스템에서 시간결정성 높은 이벤트 공유를 위한 제어프로세서 사이의 메시징 방법을 제안한다. 제안한 방법은 서비스 실행 중에 이벤트 공유를 단순화하고 이벤트 데이터에 의한 시간 가변성을 최소화하여, 글로벌 이벤트 처리의 지연 시간을 줄이고 시간결정성을 향상시킨다. 경로 이벤트 처리에 제안한 방법을 사용할 때, 738개의 경로 전환에서 일반적인 방법보다 최대 40% 의 지연 시간 감소 효과가 있다.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.85-92
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• 2009

본 논문은 시스톨릭 어레이와 덧셈기 트리를 조합한 하이브리드 구조를 갖는 MPEG-4 인코더용 전역 탐색 블록 정합 움직임 추정 회로를 제안한다. 제안된 회로는 적은 수의 클럭 싸이클로 움직임 추정을 할 수 있도록 시스톨릭 어레이를 활용하고, 필요한 회로 자원을 줄이기 위해서 덧셈기 트리를 활용한다. 1/2화소 움직임 추정을 위한 보간 회로는 6개의 덧셈기, 4개의 뺄셈기, 10개의 레지스터로 구성하였으며, 자원 공유 및 효율적인 스케줄링 기법을 통하여 성능을 향상시켰다. 정수화소 및 1/2 화소를 위한 움직임 추정 회로를 Verilog HDL을 사용하여 RTL에서 설계하였다. 130nm 표준 셀 라이브러리를 사용하여 합성한 논리 수준 회로는 218,257 게이트로 구성되었으며, D1($720{\times}480$) 이미지를 초당 94장 처리할 수 있다.

• Journal of Power Electronics
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• 제15권6호
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• pp.1429-1437
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• 2015

A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulse-width modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a three-level converter and a half-bridge converter sharing the same lagging-leg switches. A resonant capacitor is adopted on the primary side of the three-level converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional three-level converters is alleviated. A half-bridge converter is adopted to extend the ZVS range. Therefore, the lagging-leg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the three-level converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.