• Journal of Korea Society of Industrial Information Systems
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• v.8 no.2
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• pp.84-91
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• 2003

KOMPSAT series use software-controlled unregulated bus system in which the main bus is directly connected to a battery and the duty-ratio for PWM switch is controlled by the on-board satellite software. This paper proposes a new power-stage circuit that can be available for modularization of the power regulator which is used at the software-controlled unregulated bus system satellite. And we analyze the proposed power-stage operation according to its operating modes and verify it by performing software simulation and hardware experiment using prototype. We construct a parallel-module converter which is composed of proposed power-stages and perform experiment to verify modular characteristics of the proposed power-stage. Finally, we verify the usefulness of the proposed power-stage by comparing above results with those of a parallel-module converter made of conventional power-stages.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.11
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• pp.2000-2006
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• 2011

Asynchronous phenomenon occurs on the synchronous generators under power system when a generator's amplitude of electromagnetic force, phase angle, frequency and waveform etc become different from those of other synchronous generators which can follow instantly varying speed of turbine. Because the amplitude of electromagnetic force, phase frequency and waveform differ from those of other generators with which are to be put into parallel operation due to the change of excitation condition for load sharing and the sharing load change, if reactive current in the internal circuit circulates among generators, the efficiency varies and the stator winding of generators are overheated by resistance loss. Where calculation method of protection settings and Logic for Protection of Generator Asynchronization will be recommended, A distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, Zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome asynchronizing protection this paper describes an improved backup protection coordination scheme using a new Logic that will be suggested.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.6
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• pp.114-123
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• 1985

This is the second part of the four-part paper describing the development of a packet-switched computer network named the cORNET In this paper, following the first par paper that describes the concepts of the KORNET and the development of the network management center (NMC), wc present the design of the KORNET and the development of the network node processor (NNP) The initial configuration of the KORNET consists of three NNP's and one NMC. We have developed each NNP as a microprocessor-based (Mc68000) multiprocessor system, and implemented the NMC using a super-mini computer (Mv/8000) For the KORNET we use the virtual circuit (VC) method as the packet service strategy and the distributed adaptive routing algorithm to adapt efficiently the variation of node and link status. Also, we use a dynamic buffer management algorithm for efficient storage management. Thc hardware of the NNP system has been designed with emphasis on modularity so that it may be expanded esily . Also, the software of the NNP system has been developed according to the CCITT recommendations X.25, X.3, X.28 and X.29.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.3
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• pp.95-99
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• 2008

This paper proposes a new minimal resource high-level synthesis algorithm for low power design automation. The proposed algorithm executes an efficient approach to minimize the power consumption of the functional units in a circuit during the high level synthesis. In this paper, we visit all control steps one by one to reduce the switching activity in CDFG. The register sharing algorithm determines the minimum register after the life time analysis of all variable. According to property of input signal for functional unit, the proposed method visits all control step one by one and determines the resource allocation with minimal power consumption at each control step in a greedy fashion. The effect of the proposed algorithm has been proved through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low rover.

• Journal of Power Electronics
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• v.15 no.3
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• pp.610-620
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• 2015

An inherent zero-voltage and zero-current-switching phase-shifted full-bridge converter with reverse-blocking insulated-gate bipolar transistor (IGBT) or non-punch-through IGBT is proposed in this paper. This converter not only ensures that the switches in the lagging leg works at zero-current switching, but also minimizes circulating conduction loss without any additional auxiliary circuits. A 1.2 kW hardware prototype is designed, fabricated, and tested to verify the proposed topology. The control loop design procedures with small-signal models are also presented. A simple, low-cost, and robust democratic current-sharing circuit is also introduced and verified in this study. The proposed converter is a suitable alternative for compact, cost-effective applications with high-voltage input.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.3
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• pp.107-116
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• 2005

The paper addresses modeling and analysis of a grid-connected photovoltaic generation system (PV system). PSCAD/EMTDC, an industry standard simulation tool for studying the transient behavior of electric power system and apparatus, is used to conduct all aspects of model implementation and to carry out extensive simulation study. This paper is aimed at sharing with the PSCAD/EMTDC user community our user-defined model for PV system applications, which is not yet available as a standard model within PSCAD/EMTDC. An equivalent circuit model of a solar cell has been used for modeling solar array. A series of parameters required for array modeling have been estimated from general specification data of a solar module. A PWM voltage source inverter (VSI) and its current control scheme have been implemented. A maximum power point tracking (MPPT) technique is employed for drawing the maximum available energy from the PV array. Comprehensive simulation results are presented to examine PV array behaviors and PV system control performance in response to irradiation changes. In addition, dynamic responses of PV array and system to network fault conditions are simulated and analysed.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2234-2236
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• 1997

The SIT, a Static Induction Transistor, is a semiconductor switch that is also called the power junction field-effect transistor (power JFET). Its characteristics are similar to a MOSFET except that its power level is higher and its maximum frequency of operation is lower. The normal method to protect against internal circuit transients of the form of di/dt or dv/dt is the use of snubber circuits. However, the limits of di/dt and dv/dt are high enough for the SIT that it is possible to operate without snubber circuits. SITs can be connected in parallel in order to cope with higher load currents that the value of an individual device rating. The purpose of this study is to investigate the parallel operation of SITs. In this experiment, we used a half-bridge inverter, the output of inverter is up to almost 1MHz and 2kW. Experimental results show that the operation of parallel connected SITs are facilitated individually good current sharing. The reason is the positive temperature coefficient of resistance of the SIT.