• Title/Summary/Keyword: circuit diagram

Search Result 150, Processing Time 0.021 seconds

A Delta Modulation Method by Means of Pair Transistor Circuit (쌍트랜지스터 회로에 의한 정착변조방식)

  • 오현위
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.8 no.2
    • /
    • pp.24-33
    • /
    • 1971
  • A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

  • PDF

Cascaded Propagation and Reduction Techniques for Fault Binary Decision Diagram in Single-event Transient Analysis

  • Park, Jong Kang;Kim, Myoungha;Kim, Jong Tae
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.17 no.1
    • /
    • pp.65-78
    • /
    • 2017
  • Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

Polarization Behavior and Corrosion Inhibition of Copper in Acidic Chloride Solution Containing Benzotriazole

  • Sang Hee Suh;Youngjoon Suh
    • Corrosion Science and Technology
    • /
    • v.22 no.3
    • /
    • pp.137-152
    • /
    • 2023
  • Polarization behavior and corrosion inhibition of copper in acidic chloride solutions containing benzotriazole were studied. Pourbaix diagrams constructed for copper in NaCl solutions with different BTAH concentrations were used to understand the polarization behavior. Open circuit potential (OCP) depended not only on chloride concentration, but also on whether a CuBTA layer was formed on the copper surface. Only when the (pH, OCP) was located well in the CuBTA region of the Pourbaix diagram, a stable corrosion inhibiting CuBTA layer was formed, which was confirmed by X-ray Photoelectron Spectroscopy (XPS) and a long-term corrosion test. The OCP for the CuBTA layer decreased logarithmically with increasing [Cl-] activity in the solution. A minimum BTAH concentration required to form a CuBTA layer for a given NaCl concentration and pH were determined from the Pourbaix diagram. It was found that 320 ppm BTAH solution could be used to form a corrosion-inhibiting CuBTA layer inside the corrosion pit in the sprinkler copper tube, successfully reducing water leakage rate of copper tubes. These experimental results could be used to estimate water chemistry inside a corrosion pit.

Electric Properties of LB Films using Impedance Analysis of Quartz Crystal (수정진동자의 임피던스 해석에 의한 LB막의 전기적 특성)

  • Jin, Cheol-Nam;Kim, Gyeong-Hwan;Yu, Seung-Yeop;Gwon, Yeong-Su
    • The Transactions of the Korean Institute of Electrical Engineers C
    • /
    • v.48 no.7
    • /
    • pp.503-507
    • /
    • 1999
  • Quartz crystal in contact with viscoelastic medium was described directly in terms of the electrical equivalent circuit of the system. Stearic acid was used as viscoelastic medium and deposited on the surface of quartz crystal using the Langmuir-Blodgett(LB) method. Impedance properties of quartz crystal coated with LB films which were investigated by using admittance diagram and $Ζ-\theta$ plot a method of impedance analysis. When stearic acid LB film was deposited on the surface of quartz crystal, resonant frequency of quartz crystal was changed about 100 Hz/layer. This result illustrates the ability of the sensor system to detect small amounts of special gas in air.

  • PDF

A Method of Low Power VLSI Design using Modified Binary Dicision Diagram (MBDD를 이용한 저전력 VLSI설계기법)

  • Yun, Gyeong-Yong;Jeong, Deok-Jin
    • The Transactions of the Korean Institute of Electrical Engineers D
    • /
    • v.49 no.6
    • /
    • pp.316-321
    • /
    • 2000
  • In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

  • PDF

Performance of the Viterbi Decoder using Analog Parallel Processing circuit with Reference position (아날로그 병렬 처리 망을 이용한 비터비 디코더의 기준 입력 인가위치에 따른 성능 평가)

  • Kim, Hyung-Jung;Kim, In-Cheol;Lee, Wnag-Hee;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
    • /
    • 2006.10c
    • /
    • pp.378-380
    • /
    • 2006
  • A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

  • PDF

Design and farbrication of a reflective multicolor STN-LCD panel (반사형 칼라 STN-LCD 패널의 설게 및 제작)

  • 강기형;문정민;윤태훈;김재창;남기곤;이기동;이응상
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.33A no.12
    • /
    • pp.90-96
    • /
    • 1996
  • Optical conditions of a reflective multicolor STM-LCD based on the electrical control of birefrignece are analyzed on the CIE chromaticity diagram. The luminance and the area of the locus on the cIE chromaticity diagram are the two factors to be considered in the design of an LC cell to display white, red, green, and blue. The characteristics of a test cell agrees well with numerical simulation. A completed 320$\times$240 module is addressed by a designed PWM driving circuit.

  • PDF

Design and Characteristic Analysis of an 200[kW], 30000[rpm] Induction Motor for Gearless Turbo Machine (Gearless 터보기기용 200[kW], 30000[rpm] 유도전동기 설계 및 특성 해석)

  • Jo, Won-Young;Woo, Kyung-Il;Cho, Yun-Hyun
    • Journal of Advanced Marine Engineering and Technology
    • /
    • v.30 no.3
    • /
    • pp.420-427
    • /
    • 2006
  • This paper describes design and characteristic analysis of the 200[kW], 3000[rpm] induction motor for gearless turbo machine. It was designed by the loading distribution method and the results of characteristics obtained by the equivalent circuit method are compared with the results of circle diagram. To verify the validation of design 2D finite element method is used and also 3D finite element method is used to calculate the current density curve of the rotor bars when they are broken.

A Program for Short-Circuit Capacity Calculations of Low-Voltage Circuit using the VISUAL BASIC (VISUAL BASIC을 이용한 저압회로의 단락용량계산 프로그램 개발)

  • Choi, Dong-Jin
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.21 no.7
    • /
    • pp.94-102
    • /
    • 2007
  • With the recent expansion of electric capacity, troubles in the electric system threatening the stable electricity supply are rapidly increasing. However, most of the current short-circuit capacity calculations have been made manually. This research focuses on the development of a program which uses the Visual Basic. We can obtain the stability in the system diagram and the reliability of the loaded facilities by calculating an exact breaking capacity for each electric facility with this method. We expect that this research can be widely used for the design and construction of the electric facilities in the future.

Development of Superconductive Arithmetic and Logic Devices (초전도 논리연산자의 개발)

  • Kang J. H
    • Progress in Superconductivity
    • /
    • v.6 no.1
    • /
    • pp.7-12
    • /
    • 2004
  • Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

  • PDF