• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.11
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• pp.28-34
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• 2011

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we propose Griffiths' algorithm based chip-level adaptive LMMSE equalizers for HSDPA MIMO systems using D-TxAA (dual stream transmit antenna array). First, we will derive two possible structures of Griffiths' algorithm based equalizer, and then compare their performance through computer simulations in various mobile channel environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.3-8
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• 2013

In CDMA-based systems, recently, researches on chip-level equalization have been studied in order to improve receiving performance when supporting high-rate data services. In this paper, we consider a chip-level LMMSE (linear minimum mean-squared error) receiver for D-TxAA (dual stream transmit antenna array) based single stream HSDPA MIMO systems using precoding weights. First, we will derive precoding weights for maximizing the total instantaneous received power. We will also analyze the effects of both transmit delay of precoding weights and mobile velocity on chip-level LMMSE receivers, which is verified through computer simulations in various mobile channel environments.

• Journal of the Korean Association of Geographic Information Studies
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• v.8 no.4
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• pp.14-23
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• 2005

This paper proposes a method for matching two different images, especially satellite images. In the general image matching fields, when an image is compared to other image, they may have different properties on the size, contents, brightness, etc. If there is no noise in each image, in other words, they have identical pixel level and unchanged edges, the image matching method will be simple comparison between two images with pixel by pixel. However, in many applications, most of images to be matched should have much different properties. This paper proposes an efficient method for matching satellite images. This method is to match a raw satellite image with GCP chips. From this we can make a geometrically corrected image. The proposed method is based on wavelet transformation, not required any pre-processing such as histogram equalization, analysis of raw image like the traditional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.