• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.366-366
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• 2010

Simulation Program (AFORS-HET 2.4.1) was used, include the basic structure of crystalline silicon thin film as above, below Intrinsic a-Si:H films bonded symmetrical structure (Symmetrical structure) were used. Efficiency with variation of the concentration was grown by the a-Si p-type with increasing concentrations of Na, efficiency with increasing a-Si n-type of Nd Concentrations was not changed, was decreased rapidly when concentrations were decreased. Efficiency was increased when c-Si n-type of Nd concentration was increased, otherwise efficiency was decreased when concentration was decreased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.454-455
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• 2008

태양전지의 효율은 실리콘 자체의 특성에 의해서 결정 되거나 완성된 실리콘을 통해 태양전지를 제조하는 과정에서 웨이퍼의 두께와 도핑 농도의 조절을 통해 효율을 변화 시킬 수 있다. 높은 효율을 갖는 태양전지 설계를 위해 태양전지 시뮬레이터인 AFOS HET 프로그램을 이용하여 태양전지 웨이퍼 두께와 acceptor의 도핑 농도를 조절하였다. 최적화 결과 80nm ZnO, $300{\mu}m$ c-Si(p), 1nm a-Si(i), 1nm a-Si(n), $1{\mu}m$ Ag, acceptor의 도핑 농도 $7\times10^{16}cm^{-3}$ 에서 $V_{oc}$=697.7mV, $J_{sc}$=42.15mA/$cm^2$, $P_{max}$=0.0247W/$cm^2$, FF=83.51%, Eff=24.56%의 고효율을 얻을 수 있다. 본 연구를 통하여 태양전지 설계나 제조 시에 연구비를 절감할 수 있고 높은 효율의 태양전지로 접근할 수 있다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.55-60
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• 2012

In order to develop electroless-plated Nickel Phosphate (Ni-P) as a contact material for high efficient low-cost silicon solar cells, we evaluated the effect of ambient thermal annealing on the degradation behavior of interfacial adhesion energy between electroless-plated Ni-P and silicon solar cell wafers by applying 4-point bending test method. Measured interfacial adhesion energies decreased from 14.83 to 10.83 J/$m^2$ after annealing at 300 and $600^{\circ}C$, respectively. The X-ray photoelectron spectroscopy analysis suggested that the bonding interface was degraded by environmental residual oxygen, in which the oxidation inhibit the stable formation of Ni silicide phase between electroless-plated Ni-P and silicon interface.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.426-431
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• 2010

68% of the manufacturing costs of solar cell wafer can be attributed to the slurry. The recycling of slurries is mandatory for reducing the costs of manufacturing wafering production, and the disposal of industrial waste, as well as for cutting down pollution levels. Slurries are currently being recycled using the centrifuge(decanter) method. However, this method is less than optimal as it does not completely remove the fine particles, leading to low quality. Also, be cause of the incomplete separation from the oil, it causes the impurities in the dried slurries. This study aims to develope a new recycling technology that overcomes the flaws of the centrifuge by utilizing chemicals. It will provide a total solution to the crucial process of recycling slurries in the making of solar cell wafer, by increasing the efficiency and renewable rate.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.153-153
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• 2011

유리나 폴리머를 기판으로 하는 TFT(Thin film transistor), solar cell에서는 낮은 공정 온도에서($200{\sim}500^{\circ}C$) amorphous semiconductor thin film을 poly-crystal semiconductor thin film으로 결정화 시키는 기술이 매우 중요하게 대두 되고 있다. Ge은 Si에 비해 높은 carrier mobility와 낮은 녹는점을 가지므로, 비 저항이 낮을 뿐만 아니라 더 낮은 온도에서 결정화 할 수 있다. 하지만 일반적으로 쓰이는 Ge의 결정화 방법은 비교적 높은 열처리 온도를 필요로 하거나, 결정화된 원소에 남아있는 metal이 불순물 역할을 한다는 문제점, 그리고 불균일한 결정크기를 만든다는 단점이 있었다. 그 중에서도 현재 가장 많이 쓰이고 있는 MIC, MILC는 metal과 a-Ge이 접촉되는 interface나, grain boundary diffusion에 의해 핵 생성이 일어나고, 결정이 성장하는 메커니즘을 가지고 있으므로 단순 증착과 열처리 만으로는 앞서 말한 단점을 극복하는데 한계를 가지고 있다. 이에 PIII&D 장비를 이용하면, 이온 주입된 원소들이 모재와 반응 할 수 있는 표면적이 커짐으로 핵 생성을 조절 할 수 있을 뿐만 아니라, 이온 주입 시 발생하는 self annealing effect로 결정 크기까지도 조절할 수 있다. 또한 이러한 모든 process가 한 진공 장비 내에서 이루어지므로 장비의 단순화와, 공정간 단계별로 발생하는 불순물과 표면산화를 막을 수 있으므로 절연체 위에 저항이 낮고, hall mobility가 높은 poly-crystalline Ge thin film을 만들 수 있다. 본 연구에서는, 주로 핵 생성과정에서 seed를 만드는 이온주입 조건과, 결정 성장이 일어나는 증착 조건에 따라서 Ge의 결정방향과 크기가 많은 차이를 보이는데, 이는 HR-XRD(High resolution X-ray Diffractometer)와 Raman spectroscopy를 이용하여 측정 하였으며, SEM과 AFM으로 결정의 크기와 표면 거칠기를 측정하였다. 또한 Hall effect measurement를 통해 poly-crystalline thin film 의 저항과 hall mobility를 측정하였다.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.11-15
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• 2000

This paper presents a process optimization of antireflection (AR) coating on crystalline Si solar cells. Theoretical and experimental investigations were performed on a double-layer AR(DLAR) coating of MgFe$_2$/GeO$_2$. We investigated GeO$_2$ films as an AR layer because they have a proper refractive index of 2.46 and demonstrate the same lattice constant as Si substrate. RF sputter grown GeO$_2$ film showed deposition temperature strong dependence. The GeO$_2$ at 400$\^{C}$ exhibited a strong (111) preferred orientation and the lowest surface roughness of 6.87 $\AA$. Refractive index of MgFe$_2$film was measured as 1.386 for the most of growth temperature. An optimized DLAR coating showed a reflectance as low as 2.04% in the wavelengths ranged from 0.4 ㎛ to 1.1 ㎛. Solar cells with a structure of MgFe$_2$/GeO$_2$/Ag/N$\^$+//p-type Si/P$\^$+//Al were investigated with the without DLAR coatings. We achieved the efficiency of solar cells greater than 15% with 3.12% improvement with DLAR coatings. Further details about MgFe$_2$,GeO$_2$ films, and cell fabrication parameters are presented in this paper.

• Journal of the Korean Solar Energy Society
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• v.38 no.1
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• pp.45-55
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• 2018

Environmentally benign lead-free solder coated ribbon (e. g. SnCu, SnZn, SnBi${\cdots}$) has been intensively studied to interconnect cells without lead mixed ribbon (e. g. SnPb) in the crystalline silicon(c-Si) photovoltaic modules. However, high melting point (> $200^{\circ}C$) of non-lead based solder provokes increased thermo-mechanical stress during its soldering process, which causes early degradation of PV module with it. Hence, we proposed low-temperature conductive paste (CP) based tabbing method for lead-free ribbon. Modules, interconnected by the lead-free solder (SnCu) employing CP approach, exhibits similar output without increased resistivity losses at initial condition, in comparison with traditional high temperature soldering method. Moreover, 400 cycles (2,000 hour) of thermal cycle test reveals that the module integrated by CP approach withstands thermo-mechanical stress. Furthermore, this approach guarantees strong mechanical adhesion (peel strength of ~ 2 N) between cell and lead-free ribbons. Therefore, the CP based tabbing process for lead free ribbons enables to interconnect cells in c-Si PV module, without deteriorating its performance.

• Solar Energy
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• v.17 no.4
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• pp.3-11
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• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.5
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• pp.237-241
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• 2004

Amorphous silicon (a-Si) films are used in a broad range of solar cell, flat panel display, and sensor. Because of the greater ease of deposition and lower processing temperature, thin films are widely used for thin film transistors (TFTs). However, they have lower stability under the exposure of visible light and because of their low field effect mobility ($\mu$$_{FE}$ ) , less than 1 c $m^2$/Vs, they require a driving IC in the external circuits. On the other hand, polycrystalline silicon (poly-Si) thin films have superiority in $\mu$$_{FE}$ and optical stability in comparison to a-Si film. Many researches have been done to obtain high performance poly-Si because conventional methods such as excimer laser annealing, solid phase crystallization and metal induced crystallization have several difficulties to crystallize. In this paper, a new crystallization process using a molybdenum substrate has been proposed. As we use a flexible substrate, high temperature treatment and roll-to-roll process are possible. We have used a high temperature process above 75$0^{\circ}C$ to obtain poly-Si films on molybdenum substrates by a rapid thermal annealing (RTA) of the amorphous silicon (a-Si) layers. The properties of high temperature crystallized poly-Si studied, and poly-Si has been used for the fabrication of TFT. By this method, we are able to achieve high crystal volume fraction as well as high field effect mobility.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.312.2-312.2
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• 2013

태양전지에서 SiNX층은 반사방지막 역할과 표면 페시베이션의 역할을 동시에 하고 있다. SiNx에서 굴절율과 두께는 반사율과 밀접한 관계가 있으며 동시에 표면 소수캐리어 수명에도 큰 영향을 미친다. 따라서 굴절율과 두께를 조절하여 낮은 반사도와 긴 소수캐리어 수명을 가지는 SiNx 박막을 제조하여야 우수한 효율의 태양전지를 제조할 수 있다. 본 연구에서는 다양한 굴절율과 두께의 SiNx 박막을 결정질 실리콘 태양전지에 적용하여 효율과의 상관관계를 해석하였다. SiNx 박막은 PECVD장비를 이용하여 RF파워, 가스혼합량, 증착시간 등을 각각 변화시키며 형성하였다. RF 파워는 100~500 W로 변화 시켰고 혼합가스 변화는 SiH4가스와 NH3가스, Ar가스를 각각 주입하며 증착하였다. RF 파워 300W, 가스혼합량 SiH4 90sccm, NH3 26sccm, Ar 99sccm과 기판 온도 $300^{\circ}C$, 공정시간 58초에서 포면 반사율 1.09%와 굴절률 1.965, 두께 76nm를 갖는 SiNx층을 형성 할 수 있었다. SiNx층을 증착하여 셀을 제작한 결과, 개방전압: 0.612V, 전류밀도: 38.49 mA/cm2, 충실도: 75.62%, 효율: 17.82%를 얻을 수 있었다.