• 한국정보처리학회논문지
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• 제2권1호
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• pp.95-105
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• 1995

광전송에 의한 광통신 기술의 사용이 보편화 되면서 MAP 3.0규격은 광 파이버의 전송시 잡음 여유, 열악한 환경에서의 정상 동작, 안정성, 고속 전송의 장점 등으로 전송 매체로서 선택 사양에 규정하고 있다. 이러한 특성들은 제조 환경에서 광 네트워 크를 구축하는 것에 유용하다. 본 논문에서는 버스와 스타 구조의 사용을 포함한 광 패버 802.4의 MAP 네트워크 시스템 구축에 대하여 해석하고 광 패시브스타 네트워크와 FDDI 네트워크 모델을 제안 하였다. 그리고, MAP 규격의 물리 및 데이타 링크 계층 구 조에서 100 Mbps의 이중 링 구조의 FDDI 프로토콜을 제조 환경에서의 특성을 해석 하 였다. 또한 제조 환경에서 제안된 두 모델에 대하여 응용 서비스, 실시간 처리성, 토 폴로지면에서 비교하고 평가하였다.

• Journal of Electrical Engineering and Technology
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• 제1권2호
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• pp.170-176
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• 2006

This paper proposes a topological locating algorithm to determine the location of the power quality event source. This algorithm makes use of the information on the topology of the monitored network and on the direction of PQ events. As a result, the bus incidence matrix is modified using monitor location and the direction matrix is constructed. With this information, the algorithm determines the suspected locations of the PQ events. To reduce suspicious areas, it utilizes event cause and related equipment. In case of line fault event, it calculates the distance from the monitor to the location of event source. The overall algorithm is applied to the IEEE test feeder and accurately identifies the event source location.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.258_259
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• 2009

This paper describes the development of robust processor for analyzing network state in Korean Energy Management System. The important function of topology processing is to convert the switching/device model into a bus/branch model by the status of switching devices. The state estimator also provides a consistent unified solution, not only for measurement of the observable system, but also for the unobservable system. The primary function of the online power flow is to provide a highly reliable and flexible power flow solution that can be used to solve a wide variety of power systems problems. The validity of the newly developed functions has been verified through comparative simulations with the existing EMS functions, which are currently in use in the Korean power system.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1337-1344
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• 2013

This paper presents a simplified modulation strategy for the three-leg VSI fed two-winding induction motor. The strategy provides independent unbalanced voltage control for the main and auxiliary windings. This make the motor can be reversed rotation through the range of motor speed operation without limitation of voltage boost of the auxiliary winding. To study the advantages of the proposed drive, the experimental results such as voltage stresses, hysteresis band of the currents in locus, and also acoustic noise levels of the three-leg VSI are compared with those of the conventional two-leg topology. The results obviously show that the proposed technique achieves superior performance compared with the traditional scheme in case of dramatic increase of DC bus utilization, effective reduction of harmonic voltages content, and also significant enhancement of motor efficiency.

• 대한전기학회논문지:시스템및제어부문D
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• 제55권5호
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• pp.199-204
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• 2006

To develop a safety-critical network in nuclear power plants that puts more stringent requirements than the competitive commercial ones do, we establish four design criteria - deterministic communication, explicit separation/isolation structure, reliability, verification & validation. According to those design criteria, the fundamental design elements are chosen as follows - a star topology, point-to-point physical link, connection-oriented link control and fixed allocation access control. After analyzing the design elements, we also build a communication architecture with TDM (Time Division Multiplexing) bus switching scheme. Finally, We develop a DDCNet (Deterministic Data Communication Network) based on the established architecture. The DDCNet is composed of 64 nodes and guarantees the transmission bandwidth of 10Mbps and the delay of 10 msec for each node. It turns out that the DDCNet satisfies the aforementioned design criteria and can be adequately utilized for our purpose.

• 대한전기학회논문지:전력기술부문A
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• 제49권9호
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• pp.451-458
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• 2000

This paper addresses the issues of the parameter error detection and identification in electric power systems. In this paper, the parameter error identification and estimation is carried out as part of the state estimation. A two stage estimation procedure is used to detect and identify the parameter errors. The suspected parameters are identified by the WLAV state estimator as the first stage. A new WLAV state estimator adding the suspected system parameters in the state vector is used to estimate the exact value of parameter errors. Supporting examples are given by using IEEE 14 bus system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 A
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• pp.167-168
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• 2006

This paper proposes a new fault distance calculation method in the power quality (PQ) monitoring system. The proposed method calculates the fault impedance and the fault distance based on the measurement data of the PQ monitors and the information of the topology of the distribution systems. By using the iterative calculation method, the proposed method can find more exact location of the PQ events than the existing methods. The proposed method is applied to the IEEE 34 bus test feeders by using the PSCAD/EMTDC$^{TM}$.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.677-680
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• 2008

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, achieving the smallest possible number of interface lines between a timing controller and source drivers. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per one data pair is more than 800Mbps.

• Journal of Information Display
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• 제10권1호
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• pp.37-44
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• 2009

AiPi technology incorporates an embedded clock and control scheme with a point-to-point bus topology, thereby having the smallest possible number of interface lines between a timing controller and column drivers. A point-to-point architecture boosts the data rate and reduces the number of interface lines, because impedance matching can be easily achieved. An embedded clock and control scheme is implemented by means of multi-level signalling, which results in a simple clock/data recovery circuitry. A 46" AiPi-based 10-bit FHD prototype requires only 20 interface lines, compared to 38 lines for mini-LVDS. The measured maximum data rate per data pair is more than 800 Mbps.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.717-721
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• 2003

Two non-conventional HVDC converter arrangements are compared. These include the Capacitor Commutated Converter (CCC) in which series capacitors are included between the converter transformer and the valves, and the Controller Series Capacitor Converter (CSCC), based on more conventional topology, in which series capacitors are inserted between the AC filter bus and the AC network. Results show that both options have comparable steady state and transient performance. Danger of ferroresonance with the CSCC option is eliminated by controlling the amount of series compensation. The dynamic performance simulations is peformed by PSCAD/EMTDC