• 제목/요약/키워드: bus topology

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Protocol Design for Bus Network Communication between Onboard Signalling System and MMI (차상신호장치와 MMI간 버스형 네트워크 통신프로토콜 설계)

  • Kim, Seok-Heon;Han, Jae-Mun;Jung, Ji-Chan;Cho, Yong-Gee
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.2782-2786
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    • 2011
  • In this paper a protocol design for bus network communication between onboard signalling system and MMI(Man Machine Interface) will be presented and illustrated. Recently, many onboard signailling systems adopt hot standby for safety reasons. Hot standby is a method of redundancy in which the primary and secondary systems run simultaneously. It is convenient to use bus network(bus topology) in a hot standby system for communication between onboard signalling system and MMI. Because bus network is the simplest way to connect multiple clients such as onboard signalling system, MMI and etc. However, there are many problems when two clients want to transmit at the same time on the same bus. A effective protocol is necessary to solve that problems. We will describes protocol design which is useful when onboard signalling systems and MMIs are connected via RS485(Bus Network).

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Analog Controller for Battery to Stabilize DC-bus Voltage of DC-AC Microgrid

  • Dam, Duy-Hung;Lee, Hong-Hee
    • Proceedings of the KIPE Conference
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    • 2014.11a
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    • pp.66-67
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    • 2014
  • Stabilization of the DC bus voltage is an important task in DC-AC microgrid system with renewable energy source such as solar system. A battery energy storage system (BESS) has become a general solution to stabilize the DC-bus voltage in DC-AC microgrid. This paper develops the analog BESS controller which requires neither computation nor dc-bus voltage measurement, so that the system can be implemented simply and easily. Even though others methods can stabilize and control the DC-bus voltage, it has complicated structure in control and low adaptive capability. The proposed topology is simple but is able to compensate the solar source variation and stabilize the DC-bus voltage under any loads and distributed generation (DG) conditions. In addition, the design of analog controller is presented to obtain a robust system. In order to verify the effectiveness of the proposed control strategy, simulation is carried out by using PSIM software.

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Low-Power Bus Driven Floorplan for Segmented Bus Design (버스 분할 설계를 위한 저전력 버스 기반 평면계획)

  • Yoo, Jae-Min;Rim, Chong-Suk
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.134-139
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    • 2006
  • In this paper we present the Low-Power Bus Driven Floorplan(BDF) in which the bus power consumption is minimized by using a new cost function. The previously reported BDF has used the cost function which minimizes only the chid and the bus area. However, such a cost function may not consider the bus power consumption determined by the topology of a bus in case of the segmented bus design. In this paper, we formulate a new cost function which. reflects the communication frequency and the real distance between blocks in a bus to model the bus power consumption. For the Low-Power BDF with the new cost function, the experimental results show the bus power consumption cost is reduced by 11.43% on the average.

A Study on the Enhancement of Accuracy of Network Analysis Applications in Energy Management Systems (계통운영시스템 계통해석 프로그램 정확도 향상에 관한 연구)

  • Cho, Yoon-Sung
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.29 no.12
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    • pp.88-96
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    • 2015
  • This paper describes a new method for enhancing the accuracy of network analysis applications in energy management systems. Topology processing, state estimation, power flow analysis, and contingency analysis play a key factor in the stable and reliable operation of power systems. In this respect, the aim of topology processing is to provide the electrical buses and the electrical islands with the actual state of the power system as input data. The results of topology processing is used to input of other applications. New method, which includes the topology error analysis based on inconsistency check, coherency check, bus mismatch check, and outaged device check is proposed to enhance the accuracy of network analysis. The proposed methodology is conducted by energy management systems and the Korean power systems have been utilized for the test systems.

Optical Pipelined Multi-bus Interconnection Network Intrinsic Topologies

  • d'Auriol, Brian Joseph
    • ETRI Journal
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    • v.39 no.5
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    • pp.632-642
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    • 2017
  • Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

The Implementation of the IPC Network using the Reserved Bus Topology (통신 예약 버스 방식을 이용한 IPC 통신망 구성에 관한 연구)

  • 김호건;박영덕;김선형;조규섭;박병철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.1
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    • pp.28-40
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    • 1988
  • Nowadays, the needs for intelligence of communication equipments and the cost down of micro processor are showing a tendency to have multi0processor in a single system. In this paper, based on the Reserved Bus Topology which is propoed in "A study on he Communication Method between the adjacent processor", the software and hardware is designed and developed. And tha validity of this method and the utility of designed software and hardware functions are also verified through exepriments.epriments.

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A Study on the Transmission Overload Relief by Fast Switching (고속 스위칭에 의한 송전선로 과부하 해소 연구)

  • Cho, Yoon-Sung;Lee, Han-Sang;Jang, Gilsoo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.8
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    • pp.1053-1058
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    • 2013
  • Because of computational burden and complex topology of substation, a transmission overload relief using circuit-breaker switching was very complex and difficult. However, a on-line algorithm for reducing the overloads in transmission lines has made progress due to the advance of IT technology. This paper describes the methodology for alleviating the overloads in transmission lines by circuit-breaker switching. First, the severe contingency lists and substations were selected from the results of contingency analysis. Then the switch combinations are determined using circuit-breakers of the selected substation. The topology changes are limited to equipment outage, bus split, island split, bus merge and island merge. Finally, the fast screening and full analysis methods are used to analyze the overload in transmission lines. To verify the performance of the proposed methodology, we performed a comprehensive test for both test system and large-scale power systems. The results of these tests showed that the proposed methodology can accurately alleviate the overloads in transmission lines from online data and can be applied to on-line applications.

Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

  • Tarmizi, Tarmizi;Taib, Soib;Desa, M.K. Mat
    • Journal of Power Electronics
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    • v.19 no.5
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    • pp.1074-1086
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    • 2019
  • This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W ($48.3{\Omega}$) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load ($R=54{\Omega}$ dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

Development of Monitor Positioning Algorithm considering Power System Topology and Distributed Generation (분산전원과 토폴로지를 고려한 배전계통에서의 전기품질 모니터 위치 선정 기법)

  • Moon, Dae-Seong;Kim, Yun-Seong;Won, Dong-Jun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.57 no.10
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    • pp.1744-1751
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    • 2008
  • This paper presents a monitor positioning algorithm to identify the power quality event source in the distribution system with distributed generations. This algorithm determines the appropriate number of monitors and their locations considering power system topology together with distributed generation. This paper summarizes the guidelines of monitor positioning into five principles and defines the weighting factors according to the principles. To evaluate the adequacy of monitor positioning results, ambiguity indices considering monitor location and system topology are proposed. The optimal number and locations of monitors are determined from optimization routine using the weighting factors and the monitor positioning results are evaluated in terms of ambiguity indices. The algorithm is applied to IEEE 13 bus test feeder and suggests the optimal number and locations of power quality monitors. The proposed approach can realize the expert's knowledge on monitor positioning into a sophisticated automatic computing algorithm.

A Dual Buck Three-Level PV Grid-Connected Inverter

  • Ji, Baojian;Hong, Feng;Wang, Jianhua;Huang, Shengming
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.910-919
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    • 2015
  • The use of a PV grid-connected inverter with non-isolated topology and without a transformer is good for improving conversion efficiency; however, this inverter has become increasingly complicated for eliminating leakage current. To simplify the complicated architecture of traditional three-level dual buck inverters, a new dual Buck three-level PV grid-connected inverter topology is proposed. In the proposed topology, the voltage on the grounding stray capacitor is clamped by large input capacitors and is equal to half of the bus voltage; thus, leakage current can be eliminated. Unlike in the traditional topology, the current in the proposed topology passes through few elements and does not flow through the body diodes of MOSFET switches, resulting in increased efficiency. Additionally, a multi-loop control method that includes voltage-balancing control is proposed and analyzed. Both simulation and experimental results are demonstrated to verify the proposed structure and control method.