• Title/Summary/Keyword: bus matrix

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On the Structure of System Matrix of the Multimachine Systems with Constant Impedance Loads and Calculating Algorithm (다수발전기계통의 계통행렬의 구조 및 계산알고리듬에 관한 연구)

  • 권세혁;송길영
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.38 no.11
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    • pp.870-876
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    • 1989
  • A systematic procedure for the elements of system matrix is suggested for the multimachine systems with constant impedance loads. Synchronous machines are represented by either a two-axis model or a classical model. The interrelationship of submatrices of system matrix has been investigated. Once elements of one submatrix are determined, they can be used to calculate the elements of the other submatrix. This algorithm is more effective as the number of generators modeled by a two-axis model increases. It is illustrated for 9-Bus multimachine system.

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Photosensitive Black Matrix Paste for Bus Electrode of PDP

  • Woo, Chang-Min;Kim, Duck-Gon;Kim, Dong-Ju;Song, Gab-Deuk;Kim, Soon-Hak;Cho, Ho-Young;Lee, Yoon-Soo;Park, Lee-Soon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1360-1363
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    • 2007
  • The bus electrode is composed of two layers. One is the black matrix(BM) and silver layer is formed on top of black layer. The BM paste is made by mixing $Co_3O_4$ black powder with photosensitive vehicle and rheological additives. In this work we studied the effect of $Co_3O_4$ black powder and glass frit on the rheological property of photosensitive BM paste. We also examined how the size and content of black powder and glass frit affect the transmittance and reflectance of the BM layer after sintering.

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A Study of Fast Contingency Analysis Algorithm (신속한 상정사고해석 알고리즘에 관한 연구)

  • Moon, Young-Hyun
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.34 no.11
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    • pp.421-429
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    • 1985
  • With the rapid increase of contingency cases due to complication of power system, the reduction of computation time in contingency analysis has become more significant than ever before. This paper deals with the development of a fast contingency analysis algorithm by using a matrix decomposition method. The proposed matrix decomposition method of contingency analysis yields an accurate solution by using the original triangular factor table. An outstanding feature of this method is of no need of factor table modification for network changes due to contingency outages. The proposed method is also applicable to multiple contingency analysis withremarkable reduction of computation time. The algorithm has been tested for a number of single and multiple contigencies in 17-bus and 50-bus systems. The numerical results show its applicability to practical power systems.

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Study on Pressure-dependent Dynamics of Liquid Crystal in a Twisted Nematic Liquid Crystal Cell with Thin Film Transistor (TFT를 이용한 비틀린 네마틱 액정 셀에서 외부 압력에 따른 액정 동력학에 관한 연구)

  • 고재완;김미숙;정연학;김향율;이승희
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.4
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    • pp.426-431
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    • 2004
  • We have studied the pressure-dependent liquid crystal's dynamics in a twisted nematic (TN) liquid crystal panel with thin film transistor by applying an external pressure to it. When the external pressure is applied to the panel in a dark state, the disclination lines were generated as a light leakage whereas they did not appear in a simple test cell that has only pixel and common electrodes. It was because the disclination lines were Provoked by the electric field between pixel electrode and data/gate bus line for active matrix driving. Consequently, the external pressure resulted in dynamic instability of the liquid crystal so that the disclination lines at the data/gate bus line intruded into the active area.

Optimal Location of PSS and FACTS using Sensitivity Index (PSS와 FACTS의 감도기법을 이용한 위치 선정에 관한 연구)

  • Kim, Yang-Il;Ki, Kyung-Hyun;Jeung, Sung-Won;Gim, Jea-Hyeon
    • Proceedings of the KIEE Conference
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    • 2003.07a
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    • pp.221-223
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    • 2003
  • In this paper, a sensitivity index is proposed for identifying the location of FACTS in the power system with PSS. The index can be calculated by using the bus impedance matrix of the power system. This index that is related with sensitivity matrix is included in the network and not in operating condition for power system. This index is applied to IEEE 9 bus test system.

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A Study on the Optimal Power Flow Solution (최적 전력 조류 해법에 관한 연구)

  • You, Seok-Koo;Min, Pyoung-Oh
    • Proceedings of the KIEE Conference
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    • 1989.11a
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    • pp.176-179
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    • 1989
  • Newton's OPF algorithm, for each iteration, solves with second order approximation of Lagraqngian function and sparse matrix technique. When load model is applied to this technique, load voltages have tendency to be fixed at lower limit. It makes the solution inadequte. In this paper, reference bus voltage specification technique suggested to make adequate load voltage. This method is verified useful 6-bus Ward-Hale sample system.

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Universal learning network-based fuzzy control

  • Hirasawa, K.;Wu, R.;Ohbayashi, M.
    • 제어로봇시스템학회:학술대회논문집
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    • 1995.10a
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    • pp.436-439
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    • 1995
  • In this paper we present a method to construct fuzzy model with multi-dimension input membership function, which can construct fuzzy inference system on one node of the network directly. This method comes from a common framework called Universal Learning Network (ULN). The fuzzy model under the framework of ULN is called Universal Learning Network-based Fuzzy Inference System (ULNFIS), which possesses certain advantages over other networks such as neural network. We also introduce how to imitate a real system with ULN and a control scheme using ULNFIS.

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Simplified Process for Passive Matrix OLEDs

  • Lee, Seung-Jun;Sin, Yun-Su;Im, Dae-U;Yu, Jae-Hun;Choe, Gyeong-Hui
    • Proceedings of the Optical Society of Korea Conference
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    • 2008.02a
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    • pp.397-398
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    • 2008
  • We have developed simplified processes for the formation of insulators, cathode separators and bus electrodes in PMOLEDs. The insulators and cathode separators are patterned simultaneously by a single layer of image reversal photoresist. And, the bus electrodes of low resistance are formed by the cathode separator and cathode metal. Using these simplified processes, we fabricated 1.17" $96{\times}RGB{\times}96$ panels and analyzed their performance and reliability.

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A Distributed Control Method based on Voltage Sensitivity Matrix in DC Microgrids for Improvement of Power Sharing Accuracy and Voltage Regulation Performance (직류 마이크로그리드의 전력 공유 정확도 및 전압 제어 성능 향상을 위한 전압 민감도 행렬 기반의 분산 제어 방법)

  • Lee, Gi-Young;Ko, Byoung-Sun;Lee, Jae-Suk;Kim, Rae-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.23 no.5
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    • pp.345-351
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    • 2018
  • A distributed control method is proposed to improve the power sharing performance of bidirectional distributed generators and the voltage regulation performance of a DC bus in a DC microgrid. Voltage sensitivity analysis based on power flow analysis is conducted to analyze the structural characteristics of a DC microgrid. A distributed control method using a voltage sensitivity matrix is proposed on the basis of this analysis. The proposed method uses information received through the communication system and performs the droop gain variation method and voltage shift method without additional PI controllers. This approach achieves improved power sharing and voltage regulation performance without output transient states. The proposed method is implemented through a laboratory-scaled experimental system consisting of two bidirectional distributed generators, namely, a load and a non-dispatchable distributed generator in a four-bus ring-type model. The experimental results show improved power sharing accuracy and voltage regulation performance.

Fast and Accurate Performance Estimation of Bus Matrix for Multi-Processor System-on-Chip (MPSoC) (멀티 프로세서 시스템-온-칩(MPSoC)을 위한 버스 매트릭스 구조의 빠르고 정확한 성능 예측 기법)

  • Kim, Sung-Chan;Ha, Soon-Hoi
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.11
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    • pp.527-539
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    • 2008
  • This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.