• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.4
• /
• pp.49-53
• /
• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Korean Journal of Construction Engineering and Management
• /
• v.12 no.5
• /
• pp.71-80
• /
• 2011

Flying net should be installed on every 3 or 4 construction floor from 8m above ground according to the rule. In the apartment housing construction, flying net installation work has been recognized the most dangerous work among the whole works because a small mistake of labors might make their death accident. Sub-contractors specialized in flying net have been developing various flying net types. However, most works of installing flying net as working with the developed system are performed outside the apartment housing, so that the risk of fall in works of installing supports and unfolding net is still high. Furthermore, as using the previously developed flying net labors might bump into the frame or the wire rope for supporting so that it makes secondary accidents. The objective of this research is to produce the proto-type of anti-collision flying net system based on the result of problem analysis on the installation and detachment process and suggest the improved anti-collision flying net system, which is able to improve safety and field applicability by conducting field experiment and analyzing performance.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.3 s.36
• /
• pp.243-251
• /
• 2005

The distribution of temperature of flip chipped device with peripheral solder bump array was measured with variables, such as the locations and geometries of heater, the size of device, the size of passivation opening. The highest temperature was measured with the larger device, $3.0(mm)\times3.0(mm)$, which has the smallest heater at the center of device and the circular passivation opening. For 2 (watts) power input, the device shows the highest temperature of about $110(^{\circ}C)$. In contrast, the smaller device, $1.5(mm)\times1.8(mm)$, shows that of $90(^{\circ}C)$. In addition to the size effect, the increase of passivation opening size decreased the maximum temperature by about $10(^{\circ}C)$. From the measurement, the temperature of device could be controlled with the size and geometry of heater, the size of device and the size and geometry of passivation opening.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.1 s.38
• /
• pp.7-15
• /
• 2006

In-situ observation of electromigration in thin film pattern of 63Sn-37Pb solder was performed using a scanning electron microscope system. The 63Sn-37Pb solder had the incubation stage of electromigration for edge movement when the current density of $6.0{\times}10^{4}A/cm^2$ was applied the temperature between $90^{\circ}C\;and\;110^{\circ}C$. The major diffusion elements due to electromigration were Pb and Sn at temperatures of $90-110^{\circ}C\;and\;25-50^{\circ}C$, respectively, while no major diffusion of any element due to electromigration was detected when the test temperature was $70^{\circ}C$. The reason was that both the elements of Sn and Pb were migrated simultaneously under such a stress condition. The existence of the incubation stage was observed due to Pb migration before Sn migration at $90-110^{\circ}C$. Electromigration behavior of 63Sn-37Pb solder had an incubation time in common for edge drift and void nucleation, which seemed to be related the lifetime of flip chip solder bump. Diffusivity with $Z^*$(effective charges number) of Pb and Sn were strongly affect the electromigration-induced major diffusion element in SnPb solder by temperature, respectively.

• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.3
• /
• pp.29-35
• /
• 2003

The Sn-based lead-free solders with varying microstructure were prepared by changing the cooling rate from the melt. Bulky as-cast SnAg, SnAgCu, and SnCu, alloys were cold rolled and thermally stabilized before the creep tests so that there would be very small amount of microstructural change during creep (TS), and thin specimens were water quenched from the melt (WQ) to simulate microstructures of the as-reflowed solders in flip chips. Cooling rates of the WQ specimens were 140∼150 K/sec, and the resultant $\beta-Sn$ globule size was 5∼10 times smaller than that of the TS specimens. Subsequent creep tests showed that the minimum strain rate of TS specimens was about $10_2$ times higher than that of the WQ specimens. Fractographic analyses showed that creep rupture of the TS-SnAgCu specimens occurred by the nucleation of voids on the $Ag_3Sn$ Sn or $Cu_6Sn_5$ particles in the matrix, their subsequent growth by the power-law creep, and inter-linkage of microcracks to form macrocracks which led to the fast failure. On the other hand, no creep voids were found in the WQ specimens due to the mode III shear rupture coming from the thin specimens geometry.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.1 s.38
• /
• pp.23-29
• /
• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Physical Therapy Korea
• /
• v.11 no.1
• /
• pp.53-67
• /
• 2004

This simulation study investigated the characteristics of normal gait, $30^{\circ}$ crouch gait, $30^{\circ}$ crouch/equinus gait, $45^{\circ}$ crouch gait, $45^{\circ}$ crouch/equinus gait. The knee flexion angles were restricted using a specially designed orthosis. This study was carried out in a motion analysis laboratory of the National Rehabilitation Center. Fifteen healthy male subjects were recruited for the study. The purposes of this study were (1) to compare spatiotemporal parameters, kinematics, and kinetic variables in the sagittal plane among the different gait, (2) to investigate the secondary compensatory strategy, and (3) to suggest biomechanical physical therapy treatment methods. The pattern and magnitude observed in each condition were similar to those of normal gait, except the peak knee extension moment of the unrestricted ankle motion-crouch gait. However, the speed of the $45^{\circ}$ crouch gait was half that of a normal gait. The ankle joint moment in the crouch/equinus gait showed the double-bump pattern commonly observed in children with spastic cerebral palsy, and there was no significant difference in gait speed as compared with normal gait. The peak ankle plantar-flexor moment and ankle power generated during the terminal stance in the crouch/equinus conditions were reduced as compared with normal and $45^{\circ}$ crouch gaits (p<.05). The crouch/equinus gait at the ankle joint was an effective compensatory mechanism. Since ankle plantarflexion contracture can be exacerbated secondary to the ankle compensatory strategy in the crouch/equinus gait, it is necessary to increase the range of ankle dorsiflexion and the strength of plantarflexion simultaneously to decrease the abnormal biomechanical advantages of the ankle joint.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.11a
• /
• pp.123-123
• /
• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.4
• /
• pp.77-84
• /
• 2006

Surface roughness and wafer-level thickness distribution of the non-cyanide Au bumps were characterized with variations of the electroplating current density and the bath temperature. The Au bumps, electroplated at $3mA/cm^{2}\;and\;5mA/cm^{2}$, exhibited the surface roughness of $80{\sim}100nm$ without depending on the bath temperature of $40^{\circ}C\;and\;60^{\circ}C$. The Au bumps, electroplated with $8mA/cm^{2}$ at $40^{\circ}C\;and60^{\circ}C$, exhibited the surface roughness of 800nm and $80{\sim}100nm$, respectively. Wafer-level thickness deviation of the Au bumps became larger with increasing the current density from $3mA/cm^{2}\;to\;8mA/cm^{2}$. More uniform thickness distribution of the Au bumps was obtained at a bath temperature of $60^{\circ}C$ than that of $40^{\circ}C$.

• Korean Journal of Materials Research
• /
• v.5 no.6
• /
• pp.673-681
• /
• 1995

Surface morphology and preferred orientation of 20${\mu}{\textrm}{m}$ gold electrodeposit formed from aqueous solution of the sodium gold sulfite were studied in terms of current density, plating temperature and Au concentration. As the current density changed from 13.0mA/$\textrm{cm}^2$ to 4.6mA/$\textrm{cm}^2$, the solution temperature from 3$0^{\circ}C$ to 6$0^{\circ}C$, pH from 12.0 to 9.0, agitation speed from 0 rpm to 3200rpm and Au concentration from 10g/1 to 14 g/1, local Au concentration near the cathodic surface increased. With increasing the Au concentration, the surface morphology chanced from porous structure to fine-grained structure. Furthermore, it was observed that the preferred orentation of the Au layer changed from (111) to (220) upon the same variation In the Au concentration. The surface morphology and the preferred orientation of the Au layer were found to be closely related to each other.