• Korean Journal of Materials Research
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• v.8 no.8
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• pp.744-750
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• 1998

Unlike common device, MEMS(micro-electro-mechanical system) device consists of very small mechanical structures which determine the performance of the device. Because of its small mechanical structure inside. MEMS device is very sensitive to thermal stress caused by CTE(coefficient of thermal expansion) mismatch between its components. Therefore, its characteristics are affected by material properties. process temperature. and dimensions of each layer such as chip, adhesive and substrate. In this study. we investigated the change of the thermal stress in the chip attached to a substrate. With computer-aided finite element method (FEM), the computer simulation of the thermal stress was conducted on variables such as bonding material, process temperature, bonding layer thickness and die size. The commercial simulation program, ABAQUS ver5.6, was used. Subsequently 3-layer test samples were fabricated, and their degree of bending were measured by 3-D coordinate measuring machine. The experimental results were in good agreement with the simulation results. This study shows that the bonding layer could be the source of stress or act as the buffer layer for stress according to its elastic modulus and CTE. Solder adhesive layer was the source of stress due to its high elastic modulus, therefore high compressive stress was developed in the chip. And the maximum tensile stress was developed in the adhesive layer. On the other hand, polymer adhesive layer with low elastic modulus acted as buffer layer, and resulted in lower compressive stress. The maximum tensile stress was developed in the substrate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.