• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.329-332
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• 2002

The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.662-664
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• 1998

IEEE 1149.1 바운다리스캔은 보드 수준에서 고장점검 및 진단을 위한 테스트 설계기술이다. 그러나, 바운다리스캔 제어기의 특성상 테스트 패턴의 주입에서 관측까지 2.5 TCK가 소요되므로, 연결선상의 지연고장을 점검할 수 없다. 본 논문에서는 Update_DR 신호를 변경하여, 테스트 패턴 주입에서 관측까지 1 TCK가 소요되게 함으로써, 지연고장 점검을 가능하게 하는 기술을 소개한다. 나아가서, 정적인 고장점검을 위한 테스트 패턴을 개선해 지연고장 점검까지 가능하게 하는, N개의 net에 대한 2log(N+2)의 새로운 테스트패턴도 제안한다. 설계와 시뮬레이션을 통해 지연고장 점검이 가능함을 확인하였다.

• Journal of the Korean Society for Nondestructive Testing
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• v.20 no.6
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• pp.538-544
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• 2000

A phased array ultrasonic nondestructive inspection system is being developed to obtain images of the interior of steel structures by modifying a medical ultrasound imaging system. The medical system consists of 64 individual transceiver channels that can drive 128 array elements. Several modifications of the system were required mainly due to the change of sound speed. It was necessary to fabricate array transducers for steel structure and to obtain A-scan signal that is necessary for the nondestructive testing. Boundary diffraction wave model was used for the prediction of radiation beam field from array transducers, which provided guidelines to design array transducers. And a RF data acquisition board was fabricated for the A-scan signal acquisition along a selected un line within an image. For the proper beam forming in the transmission and reception for steel structure, delay time was controlled. To demonstrate the performance of the developed system and fabricated transducers, images of artificial specimens and A-scan signals for selected scan lines were obtained in a real time fashion.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.245-249
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• 2007

In this paper describes image enhancement technique using deconvolution processing for ultrasonic nondestructive testing. When flaws are detected fur B-scan or C-scan, blurring effect which is caused by the moving intervals of transducer degrades the quality of images. In addition, acquisited images suffer form speckle noise which is caused by the ultrasonic components reflected from the grain boundary of material (1,2). The deconvolution technique can restore sharp peak value or clean image from blurring signal or image. This processing is applied to C-scan image obtained from known specimen. Experimental results show that the deconvolution processing contributes to get improved the quality of C-scan images.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.51-58
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• 2016

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

• Korean Journal of Computational Design and Engineering
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• v.10 no.3
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• pp.162-167
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• 2005

A 3D solid element mesh generation algorithm was newly developed. 3D surface points of global rectangular coordinates were supplied by a 3D laser scanner. The algorithm is strait forward and simple but it generates hexahedral solid elements. Then, the surface rectangular elements were generated from the solid elements. The key of the algorithm is elimination of unnecessary elements and 3D boundary surface fitting using given 3D surface point data.

• Korean Journal of Computational Design and Engineering
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• v.13 no.6
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• pp.450-458
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• 2008

Recently, Cartesian grid approach has been popular to generate grid meshes for complex geometries in CFD (Computational Fluid Dynamics) because it is based on the non-body-fitted technique. This paper presents a method of an octree generation and boundary cell clipping using section curves for fast octree generation and elimination of redundant intersections between boundary cells and triangles from 3D triangular mesh. The proposed octree generation method uses 2D Scan-Converting line algorithm, and the clipping is done by parameterization of vertices from section curves. Experimental results provide octree generation time as well as Cut-cell clipping time of several models. The result shows that the proposed octree generation is fast and has linear relationship between grid generation time and the number of cut-cells.

• The Magazine of the IEIE
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• v.22 no.12
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• pp.93-104
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• 1995

디지탈 회로를 구현한 칩 및 보드의 시험 비용을 줄이기 위하여 사용되는 스캔 설계 기술 동향에 대하여 기술하였다. 스캔 설계 기술은 칩 수준에서 먼저 적용되기 시작하였다. 회로의 모든 플립플롭을 스캔할 수 있도록 하는 완전 스캔이 먼저 개발되었고, 최근에는 플립플롭의 일부분만 스캔할 수 있도록 하는 부분 스캔 기술이 활발하게 논의되고 있다. 한편 보드의 시험에 있어서도 보드에 실장되는 칩의 밀도가 증가되고, 표면 실장 기술이 일반화됨에 따라 종래의 시험 기술로는 충분한 시험을 거치는 것이 불가능하게 되었다. 따라서, 칩에 적용되던 기법과 유사한 스캔 설계 기술이 적용되기 시작하였다. 이를 경계 스캔(Boundary Scan)이라고 하는데, 이 기술은 80년대 후반부터 본격적으로 논의되기 시작하였다. 1990년에는 이 기술과 관련된 IEEE의 표준이 제정되어 더욱 많이 적용되는 추세에 있다. 이 논문에서는 이러한 칩 및 보드의 시험을 쉽게하기 위한 스캔 설계 기법의 배경, 발전 과정 및 기술의 내용을 소개한다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.795-798
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• 1998

IEEE1149.1 바운다리스캔은 칩과 칩간의 연결선상에서 발생가능한 지연고장을 점검 할 수 없게 설계되어있다. 칩에서 패턴을 주입하는 UpdateDR과 연결선을 통해서 전달된 결과 값을 관측하는 captureDR간의 간격이 ITCK가 되도록 UPdaeDR을 변경하는 기술보다 동작속도 및 추가영역면에서 최적임을 보여준다.