• 대한기계학회논문집B
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• 제26권12호
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• pp.1715-1721
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• 2002

Numerical analysis was conducted to characterize the gas flow field and particle deposition on a horizontal freestanding semiconductor wafer under the laminar flow field at vacuum environment. In order to calculate the properties of gas, the gas was assumed to obey the ideal gas law. The particle transport mechanisms considered were convection, Brownian diffusion and gravitational settling. The averaged particle deposition velocities and their radial distributions fnr the upper surface of the wafer were calculated from the particle concentration equation in an Eulerian frame of reference for system pressures of 1 mbar~1 atm and particle sizes of 2nm~10$^4$ nm(10 ${\mu}{\textrm}{m}$). It was observed that as the system pressure decreases, the boundary layer of gas flow becomes thicker and the deposition velocities are increased over the whole range of particle size. One thing to be noted here is that the deposition velocities are increased in the diffusion dominant particle size range with decreasing system pressure, whereas the thickness of the boundary layer is larger. This contradiction is attributed to the increase of particle mechanical mobility and the consequent increase of Brownian diffusion with decreasing the system pressure. The present numerical results showed good agreement with the results of the approximate model and the available experimental data.

• 한국실내디자인학회논문집
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• 제18권1호
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• pp.64-71
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• 2009

The modern society is rapidly changing through the development of computer network technology. By generation a collapse of boundaries between may important social institutions, computer networking has affected culture, economy and the physical environment. Because of this, people face a switchover from a simple society, to a compound society. It will also increase the diversity if society's demand, though, and experience. This change is not an exception in the exhibition space. People are more interested in civilized pastimes and also demand diverse thinking. So as a necessary consequence, the function of museum space Is offended and that there are various attempt to increase information and demand of that space. The purpose of this study is try to find a solution a countermeasure of modern society's mobile situation. Researchers analyzed structural qualities of Hyper-text; non-boundary, interaction and nonlinear and deduce nine kinds of methods to apply in space. Also, Researchers looked at the examples in museum space and derived like this expression way; dynamics, mobility, a non-materiality, continuity, complexity from analysis of expression way.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• 한국콘텐츠학회논문지
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• 제21권1호
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• pp.173-184
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• 2021

본 연구는 사회적 공정성에 대한 인식과 그로 인한 계층상승 가능성에 대한 기대감이 개인의 정서적 우울에 미치는 영향을 살펴보고, 나아가 그러한 영향력이 어떠한 조건 하에서 보다 증폭되거나 완화되는지 살펴보고자 하였다. 자신이 속한 사회의 공정성에 대한 인식이 보다 향상될수록 개인은 스스로의 계층상승에 대한 보다 낙관적 기대를 품게 되지만, 그러한 공정성에 대해 부정적으로 인식할수록 계층상승 가능성에 대해서도 보다 비관적으로 기대를 하게 될 수 있다. 아울러 이러한 기대의 저하는 계층 상승이라는 소기의 성과를 달성할 가능성이 낮다는 것을 의미함으로써 개인의 정서적 우울을 보다 심화시킬 수 있다. 그리고, 이러한 계층상승 가능성의 저하로 인한 정서적 우울의 심화는 개인의 (1)사회적 자본 및 (2)경제적 자원이 결핍되어 있을 때 보다 두드러지게 심화될 수 있다. 본 연구는 이러한 일련의 가설들에 대한 검증을 위해 한국갤럽이 한국행정연구원의 의뢰로 수집한 총 8000명에 관한 설문자료를 활용하였으며, 분석 결과 본 연구의 모형은 지지되고 있는 것으로 확인되었다. 이러한 결과는 향후 공정성 제고 및 우울증 예방에 관한 정책의 수립과 연구 모형의 정립에 있어 이론적 토대를 마련하는데 기여하여 줄 수 있을 것이다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.107-107
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• 2012

Recently, large-area synthesis of high-quality but polycrystalline graphene has been advanced as a scalable route to applications including electronic devices. The presence of grain boundaries (GBs) may be detrimental on some electronic, thermal, and mechanical properties of graphene, including reduced electronic mobility, lower thermal conductivity, and reduced ultimate mechanical strength, yet on the other hand, GBs might be beneficially exploited via controlled GB engineering. The study of graphene grains and their boundary is therefore critical for a complete understanding of this interesting material and for enabling diverse applications. I present that scanning electron diffraction in STEM mode makes possible fast and direct identification of GBs. We also demonstrate that dark field TEM imaging techniques allow facile GB imaging for high-angle tilt GBs in graphene. GB mapping is systematically carried out on large-area graphene samples via these complementary techniques. The study of the detailed atomic structure at a GB in suspended graphene uses aberration-corrected atomic resolution TEM at a low kV.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.329-329
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• 2016

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2001년도 제4회 압출 및 인발가공 심포지엄
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• pp.55-62
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• 2001

An electrolytic copper rod was drawn up to $90\%$ in area reduction and annealed under various conditions. The EBSD measurement of the drawn wire showed that in the center region the <111> + <100> fiber duplex texture was dominant, while in the middle and surface regions relatively defused textures developed with a little higher density in <11w>//wire axis. The inhomogeneous texture in the deformed wire gave rise to the inhomogeneous microstructure and texture after annealing. The annealing texture could be classified into the recrystallization texture developed during low temperatures and at the early stage at a high temperature and the growth texture developed after a prolonged annealing at the high temperature. The recrystallization temperature could be explained by the strain energy release maximization model and the growth texture was discussed based on the grain boundary mobility anisotropy.

• Journal of Ubiquitous Convergence Technology
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• 제2권2호
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• pp.97-104
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• 2008

In this paper, we demonstrate the boundary effect of a deployed regions on the effective coverage of a mobile node. A node coverage area is not uniform throughout the entire deployed region. Assuming a uniform coverage can result in significant error in calculations. In this study, we analyze the behavior of a node's coverage area as a function of its transmission range throughout the entire deployed region. Using this analysis, a mathematical model for effective coverage in mobile wireless communications is created. The mathematical model considers the effect of the deployed regions boundaries on the coverage area of a mobile node. Lastly, we present simulation results to verify the analytical model and to compare this model with that of a uniform coverage.

• 한국세라믹학회지
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• 제29권4호
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• pp.265-272
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• 1992

Role of CaO in the sintering of 12Ce-TZP ceramics was studied. The addition of small amounts of CaO increase the densification rate of 12Ce-TZP by altering lattice defect structure and the diffusion coefficient of the rate controlling species, namely cerium and zirconium cations. CaO also inhibits grain growth during sintering and allows the sintering process to proceed to theoretical density by maintaining a high diffusion flux of vacancies from the pores to the grain boundaries. The inhibition of grain growth is accomplished by the segregation of solute at the grain boundaries, causing a decrease in the grain boundary mobility. The segregation of calcium was revealed by AES study.

• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.359-363
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• 2011

To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.