• Journal of Korean Society for Atmospheric Environment
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• v.26 no.2
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• pp.107-117
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• 2010

The atmospheric geochemistry of mercury is generalls represented by gaseous elemental phase that exhibits the high environmental mobility and relatively long atmospheric residence time (c.a., 1 year) with its high chemical stability. In the recognition of the environmental significance of its global cycling, enormous efforts have been devoted to the measurements of Hg exchange across air-soil boundary. To be able to describe the fundamental aspects on this subject, the current development in the measurements of atmospheric exchange rates of mercury has been summarized using the current database reported worldwide. As a first step, different techniques commonly employed in its measurements are introduced with the discussions on their merits and disadvantages. Then, the results derived from various field measurement campaigns are also compared and discussed. The direction for the future study of mercury is presented at last.

• The Korean Journal of Ceramics
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• v.4 no.3
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• pp.207-212
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• 1998

By comparison of the experimental results in two systems of ZnO varistors, it's appear that Sb2O3 is the indispensable element for twining in ZnO varistors and the Zn7Sb2O12 spinel acts as the nucleus to form twins. Al2O3 is not the origin of twining in ZnO varistor, but it was found that Al2O3 could strengthen the twining and form a deformation twining by ZnAl2O4 dragging and pinning effect. The inhibition ratios of grain and nonuniformity of two systems ZnO varistors increase with the increase of Al2O3 content. The twins affect the inhibition of grain growth, the mechanism could be explained follow as: twins increase the mobility viscosity of ZrO grain and grain boundary, and drag ZrO grain and liquid grain boundary during the sintering, then the grain growth is inhibited and the microstructure becomes more uniform.

• Electrical & Electronic Materials
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• v.5 no.3
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• pp.310-319
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• 1992

LPCVD 방법으로 625.deg.C와 560.deg.에서 증착한 다결정 실리콘에 As이온주입량을 lx$10^{13}$-lx$10^{16}$/$cm^{2}$로 변화시키면서 열처리 전, 후의 미세구조와 전기적 특성 변화를 조사하였다. 625.deg.C에서 증착한 시편은 columnar구조를 하고 있어 표면이 매우 거칠었으며 900.deg.C, 30분 열처리 후에는 As doping 농도에 관계없이 결정립 크기는 200-300.angs.정도였다. 560.deg.C에서 증착한 시편은 비정질 상태로열처리 후에는 1000.angs.이상의 큰 결정립을 갖는 타원형의 결정립으로 성장하였으며 표면이 매우 smooth하였다. 같은 doping 농도에서 전기 전도도와 Hall mobility는 비정질 상태로 증착한 시편이 큰 결정립으로 인하여 다결정 상태로 증착한 시편에 비해 크게 되었다. Grain boundary trapping model에 의해 계산한 potential barrier height는 As doping 농도가 증가함에 따라 감소하였으며 grain boundary trap density는 증착 온도, As doping 농도 및 결정립 크기에 크게 관계없이 3.6~5*$10^{12}$/$cm^{2}$로 측정되었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.338-338
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• 2011

최근 FPD (Flat Pannel Display) 시장이 커짐에 따라 고효율, 저비용 제작 공정이 화두로 떠오르고 있다. ELA (Excimer Laser Annenling)을 이용한 LTPS (Low Temperature Poly Silicon) 공정은 mobility와 전류 점멸비 등에서 장점을 가지지만, 고비용, 대면적과 short-range에서 uniformity가 어렵다는 단점이 있다. 이를 극복하기 위한 방법으로 dLTA (diode Laser Thermal Annealing) 공정에 대한 연구가 진행되고 있다. 본 연구에서는 Flexible Display을 만들기 위한 방법으로 dLTA 공정을 진행하였다. 이 방법은 PI (Poly imide) 기판 위에 a-Si을 ICP CVD로 증착시킨 후, Diode Laser (980 nm)를 이용한 annealing을 통하여 a-Si이 poly-Si으로 결정화가 되는 것을 확인하였고, 에너지 조사량에 따른 grain boundary와 grain size을 통하여 비교 분석하였다. 실험 결과 ELA 공정을 이용한 것과 버금가는 실험 결과를 얻을 수 있었다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.6
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• pp.582-589
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• 1991

We used Cd Se as the semiconductor to analyze the Poly-TFT. Cd Se TFT is fabricated by the vacuum evaporation method and the characteristics curves of the current-voltage are obtained using the results of measurement of Cd Se TFT devices. Employing least square method and Rosenbrock algorithm, we can extract the device parameters(grain boundary mobility, trap density). The current-voltage relations calculated by extracted parameters are in good agreement with experimental results.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.292-297
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• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.85-90
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• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• The KIPS Transactions:PartC
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• v.12C no.4 s.100
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• pp.481-488
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• 2005

The Mobile W provides an efficient and scalable mechanism for host mobility within the Internet. However, the mobility implies higher security risks than static operations in fixed networks. In this paper, the Mobile IP has been adapted to allow AAA protocol that supports authentication, authorization, and accounting(AAA) for security and collection for accounting information of network usage by mobile nodes(MNs). For this goal, we Propose the boundary tone overlapped network structure while solidifying the security for the authentication of an MN. That is, the Proposed scheme delivers the session keys at the wired link for MN's security instead of the wireless one, so that it provides a fast and seamless handoff mechanism. According to the analysis of modeling result, the proposed mechanism compared to the existing session key reuse method is up to about $40\%$ better in terms of normalized surcharge for the handoff failure rate that considers handoff total time.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.71-71
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• 1999

현재 소자 제작에 응용되는 수소화된 비정질 실리콘은 PECVD 방법으로 제작하는 것이 보편적인 방법이다. 그러나 비정질 실리콘 박막 트랜지스터는 band gap edge 근처에서 국재준위가 많아 mobility가 작으며 상온에서 조차 불안정하여 신뢰성이 높지 않고, 도핑된 비정질 실리콘의 높은 비저항 등의 단점으로 인하여 고속 회로에 응용이 불가능하다. 반면 다결정질 실리콘 박막 트랜지스터는 a-Si:H TFT 에 비해 재현성이 우수하고 high resolution, high resolution, high contrast LCD에 응용할 수 있다. 하지만, 다결정 실리콘의 grain boundary로 인해 단결정에 비해 많은 defect 들이 존재하여 전도성을 감소시킨다. 따라서 Mobility를 증가시키기 위해서 grain size를 증가시키고 grain boundary 내에 존재하는 trap center를 감소시켜야 한다. 따라서 본 실험에서는 PECVD 장비로 초기 기판을 plasma 처리하여 다결정 실리콘 박막을 제작하여, 기판 처리에 대한 다결정 실리콘 박막의 성장의 특성을 조사하였다. 실험 방법으로는 PECVD 시스템을 이용하여 SiH4 gas와 H2 gas를 선택적으로 증착시키는 LBL 방법을 사용하여 $\mu$c-Si:H 박막을 제작하였다. 비정질 층을 gas plasma treatment 하여 다결정질 실리콘의 증착 initial stage 관찰을 주목적으로 관찰하였다. 다결정 실리콘 박막의 구조적 성질을 조사하기 위하여 Raman, AFM, SEM, XRD를 이용하여 grain 크기와 결정화도에 대해 측정하여 결정성장 mechanism을 관측하였다. LBL 방법으로 증착시킨 박막의 Raman 분석을 통해서 박막 증착 초기에 비정질이 증착된 후에 결정질로 상태가 변화됨을 관측할 수 있었고, SEM image를 통해서 증착 회수를 증가시키면서 grain size가 작아졌다 다시 커지는 현상을 볼 수 있었다. 이 비정질 층의 transition layer를 gas plasma 처리를 통해서 다결정 핵 형성에 영향을 관측하여 적정한 gas plasma를 통해서 다결정질 실리콘 박막 증착 공정을 단축시킬 수 있는 가능성을 짐작할 수 있었고, 또한 표면의 roughnes와 morphology를 AFM을 통하여 관측함으로써 다결정 박막의 핵 형성에 알맞은 증착 표면 특성을 분석 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.