• 대한전기학회논문지:시스템및제어부문D
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• 제52권4호
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• pp.198-204
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• 2003

In this paper, we presented a new algebraic iterative algorithm for the optimal control of the nonlinear systems. The algorithm is based on two steps. The first step transforms nonlinear optimal control problem into a sequence of linear optimal control problem using the quasilinearization method. In the second step, TPBCP(two point boundary condition problem) is solved by algebraic equations instead of differential equations using the new integral operational matrix of BPF(block pulse functions). The proposed algorithm is simple and efficient in computation for the optimal control of nonlinear systems and is less error value than that by the conventional matrix. In computer simulation, the algorithm was verified through the optimal control design of synchronous machine connected to an infinite bus.

• 한국통신학회논문지
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• 제28권3C호
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• pp.296-306
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• 2003

본 논문에서는, 무반복 복호화 알고리즘을 제안하고 이를 이용한 범용 DSP칩을 사용한 프랙탈 영상 복호화기를 설계하고 구현하였다. 무반복 복호화 알고리즘은 치역블록에 대한 정의역 블록이 고정된 Monro and Dudbridge의 알고리즘으로 부호화된 영상에 대하여 끌개영상은 해석식으로 얻을 수 있음을 보여준다. 그리고 얻어진 해석식을 이용하여 끌개영상은 반복없이 얻을 수 있었다. 또한 일반화된 식을 유도하였다. 해석식의 성능평가를 위하여, 여러 테스트 영상에 대한 해석식을 이용하는 방법과 이전의 반복적인 방법의 시뮬레이션 결과를 비교하였다. 그 결과 해석식을 이용하는 방법은 복호화 시간을 5배 이상 향상시킬 수 있었다. 제작된 프랙탈 영상 복호화기는 2개의 ADSP2181을 가지고 3단계 파이프라인 구조로 복호화 과정이 수행된다. QCIF 형식에 대한 정지영상에 대하여, 구현된 복호화기의 성능은 프레임당 최대 31.2㎳ 소요된다. 그 결과, 초당 30 frames/sec 이상의 실시간 처리 가능함을 보였다.

• 정보보호학회논문지
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• 제12권2호
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• IEIE Transactions on Smart Processing and Computing
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• 제6권3호
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• 한국멀티미디어학회논문지
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• 제19권2호
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• pp.200-208
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• 2016

Compressed sensing is a signal processing technique for efficiently acquiring and reconstructing in an under-sampled (i.e., under Nyquist rate) representation. A block compressed sensing with projected Landweber (BCS-SPL) framework is most widely known, but, it has high computational complexity at decoder side. In this paper, by introducing adaptive exit criteria instead of fixed exit criteria to SPL framework, an effective fast algorithm is designed in such a way that it can utilize efficiently the sparsity property in DCT coefficients during the iterative thresholding process. Experimental results show that the proposed algorithm results in the significant reduction of the decoding time, while providing better visual qualities than conventional algorithm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.46-49
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• 2000

An iterative deblocking algorithm for DCT-compressed images using two-dimensional FIR filters adapted for local directionality of each block, is proposed. First, we introduce a set of simple lowpass filters, which are adapted for edges of different angles. In conventional deblocking methods based on lowpass-filtering and convex projections, a single filter is applied to a whole image. In the proposed method, on the other hand, a suitable filter is chosen out of the directional filters designed previously in every subimage (typically $8{\times}8$ block). Experimental results indicate that adaptive filtering improves PSNR at each iteration.

• ETRI Journal
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• 제25권1호
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• pp.1-8
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• 2003

This paper introduces an efficient iterative decoding method for high-dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis-based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of $10^{-5}\;to\;10^{-6}$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권6호
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• pp.2446-2462
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• 2016

In this paper, a frequency domain Expectation-Maximization (EM)-based channel estimation algorithm for Space Time Block Coded-Orthogonal Frequency Division Multiplexing (STBC-OFDM) systems is investigated to support higher data rate applications in wireless communications. The computational complexity of the frequency domain EM-based channel estimation is increased when higher order constellations are used because of the ascending size of the search set space. Thus, a search set reduction algorithm is proposed to decrease the complexity without sacrificing the system performance. The performance results of the proposed algorithm is obtained in terms of Bit Error Rate (BER) and Mean Square Error (MSE) for 16QAM and 64QAM modulation schemes.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권3호
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• pp.111-116
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• 2000

In this paper, we presented a new algebraic iterative algorithm for the optimal control of the nonlinear systems. The algorithm is based on tow steps. The first step transforms optimal control problem into a sequence of linear optimal control problem using the quasilinearization method. In the second step, TPB(two point boundary condition problem) is solved by algebraic equations instead of differential equations using BPF(block pulse functions). The proposed algorithm is simple and efficient in computation for the optimal control of nonlinear systems. In computer simulation, the algorithm was verified through the optimal control design of Van del pole system and Volterra Predatory-prey system.

• 한국정보통신학회논문지
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• 제15권4호
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• pp.957-964
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• 2011

영상 안정화(image stabilization)는 흔들림이 있는 영상을 영상처리 기법으로 안정화 시키는 과정을 말한다. PA(projection algorithm)기법을 이용한 디지털 영상 안정화는 쉽게 글로벌 모션을 얻을 수 있어 많이 연구가 되어 왔다. PA기법은 실현이 간단하고 속도가 빠른 장점이 있지만 고정된 탐색범위를 사용함으로 탐색범위를 초과한 떨림을 안정화 시킬 수 없고 또한 큰 떨림을 안정화 하기위하여 탐색범위를 크게 하면 모션 추적에 참여하는 블록이 작아져 적확한 글로벌 모션을 얻지 못하게 된다. 본 논문에서는 기존의 PA기법의 단점을 해결하기 위하여 여러 가지 흔들림의 크기에 절용할 수 있는 IPA(Iterative Projection Algorithm)기법을 제안하여, 차량에서 찍은 연속된 영상 1000프레임에 적용하였을 때 기존의 알고리즘을 사용하고 서로 다른 탐색범위를 사용한 결과보다 PSNR이 최저 6.8%, 최고 28.9% 향상 되었다.