• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.932-939
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• 1998

In this paper, we analyze the performance of a multicode-CDMA system which have been proposed for the multimedia communications. The performance of a multicode-CDMA system, providing good spectrum efficiency as well as serving various bit rates, is analyzed with multipath, frequency selective, slowly fading Rayleigh channel. Also the proposed scheme adopting RAKE receiver with MRC(Maximal Ratio Combine) is advantageous to multipath channel. For a practical channel modeling, the JTC(Joint Technical Committee) recommended channel model(JTC(AIR) 23-065R6) is applied to simulation. The proposed schemehas serial-to-parallel convertor which splits input data stream of 2 Mits/s into 20 branches o 100 kbits/s. From the result of simulation, the case of RAKE receiver with 3 fingers to reduce the system complexity required the relatively large $E_{b}/N_O$ of 0 dB~1.5 dB, compared to the case of RAKE receiver with the number of path finger to keep the average error rate to be $1{\times}10^{-3}$ in channel A.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• Tuberculosis and Respiratory Diseases
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• v.78 no.4
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• pp.432-435
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• 2015

This is a report of the first South Korean case of a lung disease caused by Mycobacterium simiae. The patient was a previously healthy 52-year-old female. All serial isolates were identified as M. simiae by multi-locus sequencing analysis, based on hsp65, rpoB, 16S-23S rRNA internal transcribed spacer, and 16S rRNA fragments. A chest radiography revealed deterioration, and the follow-up sputum cultures were persistently positive, despite combination antibiotic treatment, including azithromycin, ethambutol, and rifampin. To the best of our knowledge, this is the first confirmed case of a lung disease caused by M. simiae in South Korea.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.91-94
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• 2006

KORDI(Korea Ocean Research & Development Institute) built a research vessel JANG-MOK with 40 G/T for a survey and observation of oceanographic environmental characteristics at coastal region in September 2005. This paper introduced the implementation for hardware and software of an integrated information network that loaded in JANG-MOK, and depicted the function of an integrated information network, such as an installation of ga-bit based network, RS232C serial & UDP network interface of instruments, a data logging software of measured data, Hawkeye II software for supporting the efficient survey works, and a real-time navigation viewer. In addition, we presents the another implementation method for an integrated information network of oceanographic research vessels.

• Journal of Biomedical Engineering Research
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• v.17 no.4
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• pp.449-458
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• 1996

Most of the conventional electrocardiowaphs foil to detect signals other than P-QRS-T due to the limited SNR and bandwidth. High-resolution electrocardiography(HRECG) provides better SNR and wider bandwidth for the detection of micro-potentials with higher frequency components such as vontricular late potentials(LP). We have developed a HRECG using uncorrected XYZ lead for the detection of LPs. The overall gain of the amplifier is 4000 and the bandwidth is 0.5-300Hz without using 60Hz notch filter. Three 16-bit A/D converters sample X, Y, and Z signals simultaneously with a sampling frequency of 2000Hz. Sampled data are transmitted to a PC via a DMA-controlled, optically-coupled serial communication channel. In order to further reduce the noise, we implemented a signal averaging algorithm that averaged many instances of aligned beats. The beat alignment was carried out through the use of a template matching technique that finds a location maximizing cross-correlation with a given beat tem- plate. Beat alignment error was reduced to $\pm$0.25ms. FIR high-pass filter with cut-off frequency of 40Hz was applied to remove the low frequency components of the averaged X, Y, and Z signals. QRS onset and end point were determined from the vector magnitude of the sigrlaIL and some parameters needed to detect the existence of LP were estimated. The entire system was designed for the easy application of the future research topics including the optimal lead system, filter design, new parameter extraction, etc. In the developed HRECG, without signal averaging, the noise level was less than 5$\mu$V$_rms RTI$. With signal averaging of at least 100 beats, the noise level was reduced to 0.5$\mu$V$_rms RTI$, which is low enough to detect LPs. The developed HRECG will provide a new advanced functionality to interpretive ECG analyzers.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.13 no.4
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• pp.139-149
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• 2003

In this paper a hardware design of area-efficient hash processor which implements MD5 algorithm using hardware sharing and carry-save addition schemes is described. To reduce area, the processor adopts hardware sharing scheme in which 1 step operation is divided into 2 substeps and then each substep is executed using the same hardware. Also to increase clock frequency, three serial additions of substep operation are transformed into two carry-save additions and one carry propagation addition. The MD5 hash processor is designed using 0.25 $\mu\textrm{m}$CMOS technology and consists of about 13,000 gates. From timing simulation results, the designed MD5 hash processor has 465 Mbps hash rates for 512-bit input message data under 120 MHz operating frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.3 s.345
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• pp.59-67
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• 2006

OFDM (Orthogonal frequency Division Multiplexing) systems convert serial data stream to N parallel data streams and modulate them to N orthogonal subcarriers. Thus spectrum utilization efficiency of the OFDM systems are high and high-speed data transmission is possible. However, with the OFDM systems using the same modulation method at all subcarriers, the error probability is dominated by the subcarriers which experience deep fades. Therefore, in order to enhance the performance of the system adaptive modulation is required, with which the modulation methods of the subcarriers are determined according to the estimated SNRs. The IEEE 802.11a system selects various transmission speed between 6 and 54 Mbps according to the modulation mode. There are three typical methods for SNR estimation: Direct estimation method uses the frequency domain symbols to estimate SNR directly by minimizing MSE (Mean Square Error), EVM method utilizes the distance between the demodulated constellation points and received complex values, and the method utilizing the Viterbi algorithm uses the cumulative minimum distance in decoding process to estimate the SNR indirectly. Through comparison analyses of three methods we propose a new SNR estimation method, which employs both the EVM method and the Viterbi algorithm. Finally, we perform extensive computer simulations to confirm the performance improvement of the proposed adaptive OFDM systems on the basis of IEEE 802.11a.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.