• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.5
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• pp.353-363
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• 1990

This paper analyzes effect of Data Bit Jitter(DBJ) on the Bit Slip Rate(BSR) of the receiver Data Tracking Loop(DTL). In particular, we point out the characteristic jitter parameters that can be used to estimate the BSR performance for the low frequency parts respectively. We also propose a new format for the DBJ specification, which is more sophisticated than the conventional method but is believed to be more practical and accurate in predicting DBJ effect on the receiver BSR performance. In the proposed method, receive dependent parameters are identified and weighting between different parts of jitter spectrum are properly considered.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.214-216
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• 2012

BIT(Built-in Test)란 소프트웨어와 하드웨어의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 빠른 오류 대처가 있어야 하는 다양한 분야에서 사용되고 있다. 현업에서의 BIT는 도메인의 특성에 따라 고려해야 하는 요소가 많으므로 각 도메인에 맞춰 구조화되지 않은 형태로 개발되고 있다. 따라서 기존 개발 방법론은 반복적인 작업이 수반되며 적용 환경 및 상활에 따라 변화하는 부분을 매번 새로 개발하기 위해 많은 인력과 시간이 필요하다는 문제점을 가진다. 이를 해결하기 위하여 본 논문에서는 개선된 BIT 개발 프로세스를 제안한다. 제안하는 프로세스는 BIT 처리 과정을 일반화하여 명세하고 이를 활용하여 BIT 처리 코트를 자동 생성한다. 그리고 BIT 코드를 검증할 수 있는 시뮬레이션 환경을 제공한다. 이를 통해 BIT 처리 구조 개발 과정의 편의성과 생산성을 향상하고 BIT 처리 구조의 유연성과 확장성 그리고 안정성을 높일 수 있다.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.175-179
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• 2005

A novel, simple and broadband $180^{\circ}$ bit X-band phase shifter was proposed and fabricated in a standard micromachining process. It is composed of two $90^{\circ}$ parallel-coupled lines; one of which is shorted and the other is grounded. Design equations for the proposed $180^{\circ}$ bit phase shifter are derived by the method of even and odd mode analysis. Based on design equations, $180^{\circ}$ bit phase shifter was designed and fabricated to operate from 7 to 13 GHz with ${\pm}5^{\circ}$ of phase deviation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.624-632
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• 2005

We consider an adaptive bit-loading technique for bit interleaved coded modulation-orthogonal frequency division multiplexing(BICM-OFDM) systems. By adjusting transmission parameter of each subcarrier adaptively depending on the subchannel state, the performance of OFDM system can be improved dramatically. In this paper, the number of bits for each subcarrier is allocated to minimize bit error rate keeping the constant throughput for the adaptive transmission technique of BICM-OFDM system which can be applied to real time transmission. Also, We use the discrete Lagrange multiplier method to get the optimum solution under the integer bit allocation constraint. Simulation results show that computational amount of the proposed bit allocation technique is not high and BICM-OfDM system using the proposed technique can get the SNR gain by 2$\~$3 dB over nonadaptive one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12B
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• pp.1091-1099
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• 2003

Korea National Intelligence Service has been issued on K4 Firewall Certificates, and these K4 Firewalls has b een installing all Korean public organizer. I would evaluate the performance tests between the before setting and the after setting of Packet Filtering, NAT, Proxy, and Authentication services on functions of Solaris K4 Firewall System. Also I had been created by performance test between existing 32 bit and latest 64 bit K4 Firewall System on Solaris Operating System, So that the result of improved more two times passed rate on 64bit than 32bit on Solaris K4 Firewall System, At finally, I would conclude that the change direction will be useful for research and development on K4 Firewall System and Korean Firewall System which is a very competitive system in the world.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.1208-1210
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• 2012

BIT(Built-In Test)란 S/W 또는 H/W 의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 기능에 대한 신뢰성 및 빠른 오류 복구를 보장하기 때문에 다양한 분야에서 BIT 처리를 통해 시스템의 안정성을 높이고 있다. 현업에서의 BIT 는 도메인 특성에 따라 처리해야 하는 작업의 변화가 크기 때문에 구조화 되지 않은 형태로 각각 개발되고 있다. 따라서 BIT 개발 시 반복적인 작업이 수반되며 처리 과정의 수정 또는 처리 범위의 확장을 위해서는 많은 시간 및 인력이 요구된다. 이에 본 논문에서는 BIT 처리를 구조화하기 위하여 처리과정에 필요한 정보들을 일반화된 형태로 기록할 수 있도록 하는 BIT 처리 병세 방안과 BIT 처리 명세를 기반으로 한 자동 코드 생성 체계를 제안한다. 이를 통해 개발 과정의 편의성과 생산성을 향상하고 BIT 처리의 유연성과 확장성을 높일 수 있다.

• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.