• Title/Summary/Keyword: bit

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Implementation of The LED illuminance control IP based on 8bit RISC Processor (8bit RISC 프로세서를 이용한 LED Array의 조도제어 IP 구현)

  • Oh, Eun-Tack;Moon, Chul-Hong
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.603-604
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    • 2008
  • This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.

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A study on improvement of SPIHT algorithm using redundancy bit removing (중복비트 제거를 이용한 SPIHT알고리즘의 개선에 관한 연구)

  • 설경호;이원효;고기영;김태형;김두영
    • Proceedings of the IEEK Conference
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    • 2003.07e
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    • pp.1920-1923
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    • 2003
  • This paper presents compression rate improvement for SPIHT algorithm though redundancy bit removing. Proposed SPIHT algorithm uses a method to select of optimized threshold from feature of wavelet transform coefficients and removes sign bit if coefficient of LL area. Experimental results show that the proposed algorithm achieves more improvement bit rate and more fast progressive transmission with low bit rate.

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A bit-rate control of MPEG-2 using linear average step quantization (선형 평균스텝 양자화를 사용한 MPEG-2 비트율 제어)

  • 이두열;이근영
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.9
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    • pp.84-90
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    • 1997
  • We proposed a new bit-rate control algorithm to improve MPEG-2 video software encoder. Bit-rate Control plays an improtant role in picture quality of MPEG-2 encoder. To achieve better encoding performance such as controlling picture quality and using bity properly, we proposed a MPEG-2 bit-rate control algorithm using linear average Step-Size. Using a benchmark Program, we compared our algorithm with MPEG-2 Test Model 5. Our proposed algorithm showed better Bit-Rate Control with respect to used bits, picture quality.

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Error Correcting Technique with the Use of a Parity Check Bit (패리티 검사비트를 이용한 새로운 오류정정 기술)

  • 현종식;한영열
    • Proceedings of the Korea Society for Industrial Systems Conference
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    • 1997.11a
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    • pp.137-146
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    • 1997
  • The simplest bit error detection scheme is to append a parity bit to the end of a bit sequence. In this paper an error correction technique with the use of a parity bit is proposed, and the performance of the proposed system is analyzed. The error probability of the proposed system is compared with the output of computer simulation of the proposed system. It is also compared with the error probability of error at BPSK system, and the signal-to-noise ratio gain is showed.

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Analysis of Transmission Performance of Communication Security Bit Synchronization Information in VMF System (가변메시지형식체계에서 통신보안을 위한 비트동기 정보의 전송영향 분석)

  • Park Youngmi;Son Youngho;Yoon Janghong;Hong Jinkeun
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.54 no.7
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    • pp.443-446
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    • 2005
  • In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel ground and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in 10-1 $\~$ 10-5 of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

A Study oil the Next-bit Test (Next-bit 검정 방법 분석)

  • 강주성;박상우;박춘식
    • Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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    • 1998.12a
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    • pp.345-353
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    • 1998
  • 본 논문에서는 next-bit 검정의 이론적 배경을 고찰하고, 실제적인 검정법으로 구현된 검정방법에 대하여 조사 분석한다. Next-bit 검정 이론은 Schrift와 Shamir가 제시한 다양한 검정방법을 중심으로 소개한다. 그리고 구현된 통계적 검정 방법은 ACISP'96에서 발표된 검정법과 CISC'97에서 제안된 검정법을 비교 분석한다.

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Design and Implementation of Bus for 32-bit RISC Microprocessor (32-bit RISC마이크로프로세서를 위한 버스 설계 및 구현)

  • 양동훈;곽승호;이문기
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.333-336
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    • 2002
  • This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

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Implementations and analysis to extract information on a bit-mapped image (Bit-mapped 이미지 상의 정보 추출의 구현 및 분석)

  • 김민호;송인희
    • Proceedings of the Korean Information Science Society Conference
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    • 2001.04b
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    • pp.562-564
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    • 2001
  • Bit-mapped형태로 저장되어진 측량 정보에서 원하는 정보를 추출하는 것은 여전히 중요하고 해 볼 만한 문제이다. 본 논문에서는 bit-mapped화 된 지도 이미지에서 주어진 두 지점간의 경로를 다양한 종류의 search 기법으로 추적하여 비교 분석하였다.

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