• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.209-216
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• 1996

In this paper, we propose a learning method of multi-layer perceptrons (MLPs) with 8-bit data precision. The suggested method uses the cross-entropy cost function to remove the slope term of error signal in output layer. To decrease the possibility of overflows, we use 16-bit weighted sum results into the 8-bit data with appropriate range. In the forwared propagation, the range for bit-conversion is determined using the saturation property of sigmoid function. In the backwared propagation, the range for bit-conversion is derived using the probability density function of back-propagated signal. In a simulation study to classify hadwritten digits in the CEDAR database, our method shows similar generalization performance to the error back-propagation learning with 16-bit precision.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.306-317
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• 1997

This ppaer presents a bit-rate conversion system for efficient communications between 3 channel CVSD systems with different bit-rates. The proposed conversion system is implemented in the digital domain and specially, the conversion problem between 32 Kbps and 16 Kbps CVSD systems is studied. The conventional conversion system implemented in the analog domain allows signals to be easily degraded by external noises. To overcome this problem, a digital CVSD bit-rate conversion system robust to external noises is developed. the new systemdecodes CVSD bit sequences and converts sampling rates of decoded signals, then encodes signals at target bit-rates. Since linear phase property does not matter in this application, instead of FIR filters a IIR filter is employed to reduce the system complexity. Therefore, a 3 channel digital CVSD bit-rate conversion system was successfully real-time implemented using a general purpose DSP. In addition, conversion problems with unkown time constants were experimented and good experimental results were obtained.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.210-216
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• 2000

The features of bit error rate (BER) are discussed, how to analyze statistics of the bit error rate. How many will the BER be improved after correcting one single-error in the block\ulcorner The answer is satisfactory in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.117-120
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• 2005

The SONOS devices have been fabricated by the conventional $0.35{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with NOR array. Two-bit operation using conventional process achieve the high density memory compare with other two-bit memory. Lateral diffusion phenomenon in the two-bit operation cause soft error in the memory. In this study, the programming conditions arc investigated in order to reduce lateral diffusion for two-bit operation of CSL-NOR type SONOS flash cell.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.241-244
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• 2000

In this paper we designed a simple 8-bit processor using HDL. The simple 13-bit processor has 19 instructions with three different addressing modes. The processor includes registers - IR, PC, SP, Y, MA, MD, AC, IN, OUT - and 256Kbyte memory. We examined the operation of the processor through simulation and then synthesized it on FPGA.

• ETRI Journal
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• v.41 no.2
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• pp.184-196
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• 2019

Wavelet packet modulation (WPM) is a multicarrier modulation (MCM) technique that has emerged as a potential alternative to the widely used orthogonal frequency-division multiplexing (OFDM) method. Because WPM has overlapped symbols, equalization cannot rely on the use of the cyclic prefix (CP), which is used in OFDM. This study applies linear minimum mean-square error (MMSE) equalization in the time domain instead of in the frequency domain to achieve low computational complexity. With a modest equalizer filter length, the imperfection of MMSE equalization results in subcarrier attenuation and noise amplification, which are considered in the development of a bit-loading algorithm. Analytical expressions for the bit error rate (BER) performance are derived and validated using simulation results. A performance evaluation is carried out in different test scenarios as per Recommendation ITU-R M.1225. Numerical results show that WPM with equalization-aware bit loading outperforms OFDM with bit loading. Because previous comparisons between WPM and OFDM did not include bit loading, the results obtained provide additional evidence of the benefits of WPM over OFDM.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.4
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• pp.1296-1309
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• 2023

In this paper, based on the soft cancellation (SCAN) bit-flipping (SCAN-BF) algorithm, a generalized SCAN bit-flipping (GSCAN-BF-Ω) decoding algorithm is carried out, where Ω represents the number of bits flipped or corrected at the same time. GSCAN-BF-Ω algorithm corrects the prior information of the code bits and flips the prior information of the unreliable information bits simultaneously to improve the block error rate (BLER) performance. Then, a joint threshold scheme for the GSCAN-BF-2 decoding algorithm is proposed to reduce the average decoding complexity by considering both the bit channel quality and the reliability of the coded bits. Simulation results show that the GSCAN-BF-Ω decoding algorithm reduces the average decoding latency while getting performance gains compared to the common multiple SCAN bit-flipping decoding algorithm. And the GSCAN-BF-2 decoding algorithm with the joint threshold reduces the average decoding latency further by approximately 50% with only a slight performance loss compared to the GSCAN-BF-2 decoding algorithm.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.272-274
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel found and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in $10^{-1}\sim10^{-5}$ of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.3C
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• pp.240-246
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• 2008

An MPEG-2/4 AAC decoder on 16-bit fixed-point processor is presented in this paper. To meet audio quality criteria, despite small word length, special design methods for 16-bit foxed-point AAC decoder were devised. This paper presents particular algorithms for 16-bit AAC decoding. We have implemented an efficient AAC decoder using the proposed algorithms. Audio contents can be replayed in the decoder without quality degradation.