• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.10
• /
• pp.4359-4364
• /
• 2012

In this study, we carried out finite element analysis for drill bit design on ground boring. We verified analysis between drill bit analysis results and experiment results of test machine. From the study, the results expect that time and cost reduction for experiment using finite element analysis for determination on drill bit geometry and material property.

• ETRI Journal
• /
• v.24 no.6
• /
• pp.462-464
• /
• 2002

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.266-269
• /
• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.533-536
• /
• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• Journal of the Korea Society of Computer and Information
• /
• v.23 no.8
• /
• pp.75-84
• /
• 2018

In this research, a bit correction technique of data hiding method in timestamp of MFT entry in NTFS file system is proposed. This method is proposed in two ways, depending on the number of bytes of data to hide. A basic data hiding method using a bit correction technique to solve the problems of the conventional 2-byte technique is proposed. In order to increase the capacity of the data, a 3-byte data hiding method using an extended bit correction technique is proposed. The data hiding method in the timestamps is based on the fact that is not revealed in the Windows explorer window and the command prompt window even if any data is hidden in the timestamp area of less than one second. It is shown that the validity of the proposed method through the experimental two cases of the basic data hiding method by the bit correction method and the 3-byte data hiding method by the extended bit correction method.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.2 no.3
• /
• pp.163-167
• /
• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.75-78
• /
• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.51-51
• /
• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.17 no.3
• /
• pp.336-341
• /
• 2014

When using a higher-order modulation scheme, there are variations in bit-reliability depending on the bit position in a modulation symbol. Variations of bit-reliability in the codeword block lower the decoding performance. Also, the decoding performance increases as the sum of the bit-reliabilities in the codeword block increases. This paper presents a novel hybrid automatic repeat request scheme that increases the sum of the reliabilities of the transmitted bits by lowering the modulation order, and decreases the variations of bit-reliability in the codeword block by preferentially retransmitting bits with low reliability. The proposed scheme outperforms the constellation rearrangement scheme. Furthermore, the proposed scheme also provides a good solution in cases where the size of the retransmission block is smaller than the size of the initial transmission block.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.45-48
• /
• 2003

In general, speech coding methods are classified into the following three categories: the waveform coding, the source coding and the hybrid coding. Fast speaking is possible to encode with a few information compared with slow speaking rate. In case of speaking rate, low frequency band is more important than high frequency band while listening. Speech vocoding technique is developing to way with low bit rate and complexity and high sound quality. the CELP type of vocoder support very good sound quality with low bit rate but these vocoders don't consider about the speaking rate. When we consider speaking rate and encode the frame depending on the speaking rate, the bit rate is able to reduce the bit rate than the conventional vocoder. We propose the technique to estimate the speaking rate and applied PSOLA technique in case of the frame of slow speaking rate. As a result of simulation bit rate can be reduced about 300 bps.