• 전자공학회논문지 IE
• /
• v.43 no.4
• /
• pp.115-121
• /
• 2006

In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

• The Journal of the Korea Contents Association
• /
• v.7 no.2
• /
• pp.92-99
• /
• 2007

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.3
• /
• pp.205-210
• /
• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.143-146
• /
• 2011

A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

• Journal of Communications and Networks
• /
• v.12 no.2
• /
• pp.103-113
• /
• 2010

In this paper, a tradeoff between the total energy consumption-per-bit and the end-to-end rate under spatial reuse in wireless multi-hop network is developed and analyzed. The end-to-end rate of the network is the number of information bits transmitted (end-to-end) per channel use by any node in the network that is forwarding the data. In order to increase the bandwidth efficiency, spatial reuse is considered whereby simultaneous relay transmissions are allowed provided there is a minimum separation between such transmitters. The total energy consumption-per-bit includes the energy transmitted and the energy consumed by the receiver to process (demodulate and decoder) the received signal. The total energy consumption-per-bit is normalized by the distance between a source-destination pair in order to be consistent with a direct (single-hop) communication network. Lower bounds on this energy-bandwidth tradeoff are analyzed using convex optimization methods. For a given location of relays, it is shown that the total energy consumption-per-bit is minimized by optimally selecting the end-to-end rate. It is also demonstrated that spatial reuse can improve the bandwidth efficiency for a given total energy consumption-per-bit. However, at the rate that minimizes the total energy consumption-per-bit, spatial reuse does not provide lower energy consumption-per-bit compared to the case without spatial reuse. This is because spatial reuse requires more receiver energy consumption at a given end-to-end rate. Such degraded energy efficiency can be compensated by varying the minimum separation of hops between simultaneous transmitters. In the case of equi-spaced relays, analytical results for the energy-bandwidth tradeoff are provided and it is shown that the minimum energy consumption-per-bit decreases linearly with the end-to-end distance.

• Journal of Korea Multimedia Society
• /
• v.9 no.2
• /
• pp.244-254
• /
• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Journal of Broadcast Engineering
• /
• v.18 no.2
• /
• pp.297-310
• /
• 2013

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a subjective quality in many video streaming services limited by network bandwidth, such as IPTV services. First, we extract major parameters which serve as an indirect measurement of frame's bits. Using those parameters, the proposed bit rate estimation scheme can extract candidate frames. Finally, the bit rate of each segment is estimated by statistical analysis and a mathematical model based on a given target quality. In experimental results, we show that the proposed scheme can reduce the bit rate on average by 43% in low-complexity video while maintaining the subjective quality. To find the appropriate bit rate based on video contents, the proposed schemes can estimate the bit rate with neither the repeated full encoding nor subjective quality test. On average, the bit rate can be automatically estimated by encoding the candidate frames of 4%.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.46 no.2
• /
• pp.18-26
• /
• 2009

When channel state information (CSI) is available at the transmitter, the system throughput can be enhanced by adaptive transmissions and opportunistic multiuser scheduling. In this paper, we consider multiple-input multiple-output (MIMO) systems employing bit-interleaved coded orthogonal frequency division multiplexing (BIC-OFDM). We first propose a bit-loading algorithm based on the Levin-Campello algorithm for the BIC-OFDM. Then we will apply this algorithm to the MIMO system with a finite set of constellations, by reassigning residual power on each stream Simulation results show that proposed bit-loading scheme which takes the residual power into account improves the system performance especially at high signal-to-noise ratio (SNR) range.

• Journal of KIISE:Databases
• /
• v.31 no.3
• /
• pp.331-339
• /
• 2004

XML has got to be a new standard for data representation and exchanging by its many good points, and the core part of many new researches and emerging technologies. However, the self-describing characteristic, which is one of XML's good points, caused the spreading of XML documents with different structures, and so the need of the research for the effective XML-document search has been proposed. This paper is for the analysis of the problem in BitCube, which is a bitmap indexing that shows high performance grounded on its fast retrieval. In addition, to resolve the problem of BitCube, we did design and implement xPlaneb(XML Plane Web) which it a new 3-dimensional bitmap indexing made of linked lists. We propose an effective information retrieval technique by replacing BitCube operations with new ones and reconstructing 3-dimensional array index of BitCube with effective nodes. Performance evaluation shows that the proposed technique is better than BitCube, as the amount of document increases, in terms of memory consumptions and operation speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.286-288
• /
• 2012

파일 공유를 위해 널리 사용되는 BitTorrent는 대표적인 P2P 프로토콜이다. BitTorrent는 전송을 요구한 클라이언트가 작은 단위로 쪼개진 하나의 파일을 다수의 클라이언트들로부터 받는 방식으로 기존의 일대일 P2P 전송방식에 대비하여 빠른 다운로드 속도를 낼 수 있다. 이러한 다운로드 성능을 발휘하기위해 다수의 조각으로 분리 된 파일 조각을 선택하는 Pieces Selection 기법은 매우 중요하다. 이에 본 논문에서는 BitTorrent에서 활용되는 네 가지의 Pieces Selection 기법에 대해 알아보고, 성능 개선을 위한 새로운 기법을 제안한다.