• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.112-116
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• 2002

In this paper, the active integrated antenna(AIA) using a wideband printed dipole antenna and a balanced amplifier is designed and fabricated. The proposed active printed dipole antenna has characteristics of easy matching, wide bandwidth and higher output power To feed balanced signal to printed dipole, a Wilkinson power divider and delay lines are used. The measured result shows that, at 6 GHz center frequency, the impedance bandwidth is 22 % (VSWR < 2), 3 dB gain bandwidth is 28 %, the maximum gain is 14.77 dBi, and output power at P1 dB point is 23 dBm.

• Journal of Power Electronics
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• v.19 no.1
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• pp.99-107
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• 2019

This study proposes a new modulation strategy to deal with unbalanced output voltage that is based on three-level neutral-point-clamped cascaded rectifiers. The fundament idea is to reallocate the value of the voltage levels generated by each of the modules on the basis of space vector pulse width modulation. This proposed modulation strategy can reduce the switching frequency while maintaining the mutual-module voltage balance. First, an analysis of unbalanced output voltage is reflected. Then a new modulation strategy is introduced in detail. Internal module capacitor voltages are balanced by the selection of redundant vectors. Moreover, the voltage balance ability is calculated. Finally, the feasibility of this modulation strategy is verified through experimental results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.764-768
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• 2002

In this paper, a double balanced gilbert cell MMIC mixer was realized in Tachyonics SiGe HBT technology. The fabricated mixer has 17 dB conversion gain, 9.8 dB noise figure, -4.2 dBm output 1 dB compression point, -27 dBc RF to IF isolation, and the good input, output matching characteristics. It draws 10 mA from a 3 V supply. The simulation and the measured results are closer to each other, which confirms accuracy of the model library and reliability of the process.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1108-1110
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• 1995

This paper presents a balanced CMOS complementary folded cascode OP-AMP topology that achieves improved DC gain using the gain boosting technique, a high unity-gain frequency and improved slew rate using the CMOS complementary cascode structure and a high PSRR using the balanced output stage. Bode-plot measurements of a balanced CMOS complementary folded cascode OP-AMP show a DC gain of 80dB, a unity-gain frequency of 110MHz and a slew rate of $274V/{\mu}s$(1pF load). This balanced CMOS complementary folded cascode OP-AMP is well suited for high frequency analog signal processing applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.192-197
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• 2009

This paper presents the design and measurement of a 2.4/5.2-GHz dual band VCO with a balanced frequency doubler in $0.18\;{\mu}m$ CMOS process. The topology of a 2.4 GHz VCO is a cross-coupled VCO with a LC tank and the frequency of the VCO is doubled by a frequency balanced doubler for a 5.2 GHz VCO. The gate bias matching network for class B operation in the balanced doubler is adopted to obtain as much power at 2nd harmonic output as possible. The average output powers of the 2.4 GHz and 5.2 GHz VCOs are -12 dBm and -13 dBm, respectively, the doubled VCO has fundamental harmonic suppression of -25 dB. The measured phase noises at 5 MHz frequency offset are -123 dBc /Hz from 2.6 GHz and -118 dBc /Hz from 5.1 GHz. The total size of the dual band VCO is $1.0\;mm{\times}0.9\;mm$ including pads.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.143-149
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• 2004

This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.107-112
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• 2007

A new impedance transforming balun scheme is presented based on the branch-line structure with stubs on the vertical branches. The stubbed vertical branch eliminates the unwanted even mode output and provides only the balanced output of the balun with opposite phase. Also, the use of stubs reduces the branch lengths by two times the stub length, which is useful for the compact balun design.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.928-931
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• 2017

This paper presents a 2 GHz pulse generator in balanced configuration for ground penetrating radar(GPR). In order to improve the input and output matching, the pulse generator is designed in balanced configuration with $90^{\circ}$ hybrid couplers. The designed pulse generator was fabricated using PCB process. The fabricated pulse generator draws 1 mA current from a 5 V power supply with 27.6 % efficiency. The measured output voltage swing is $3.7V_{pp}$ at 100 MHz pulse repetition frequency(PRF). The pulse width is 2 ns and the input and output return loss is more than 10 dB at the operating frequency of 1.7~2.6 GHz.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.431-440
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• 1989

This paper proposes a new PWM cycloconverter which can step up input voltage. With input reactors ac power supply acts as current source, and with output capacitors the balanced output voltage is build-up. The converter is modeled with fourth order state equation using dq transformation and the steady state characteristics are evaluated. It is shown that the proposed converter can generate the output voltage 2-5 times greater than input voltage. The output voltage and input current have sinusoidal and smooth waveforms and the converter is capable of voltage build-up. The characteristics of the proposed converter is verified simulation and experiment.